Some useful documents of Synopsys

Documents for ARM

低功耗设计_docs

Synopsys Design compiler, VCS and Tetra-MAX

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

Verilog implementation of multi-stage 32-bit RISC-V processor

Synthesizable R10000 style 3-way super-scalar out-of-order processor based on subset of RISC-V ISA

数字IC相关资料

Lab2 of AI computing Architecture and System (2024 spring) around Pytorch, ONNX using Python and C++

IC Contest

Python tool for converting files and office documents to Markdown.

The book "Performance Analysis and Tuning on Modern CPU"

RISC-V Linux SoC, marchID: 0x2b

Contains the code examples from The UVM Primer Book sorted by chapters.

Quantized Training for Convolutional Neural Networks using Xilinx Brevitas

Dataflow compiler for QNN inference on FPGAs

cse142ucsd-2024su-2024su-cse142-cse142l-processor-2024su-cse142-142L-processor-starter created by GitHub Classroom

RISC-V ISA based 32-bit processor written in HLS

A 3-way superscalar Out-of-Order machine with P6 style register renaming

EECS 470 Final Project

Berkeley's Spatial Array Generator

A Full Hardware Real-Time Ray-Tracer

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform