dts/riscv/microchip: add missing cpu nodes compats in mpfs.dtsi

The cores used in the `mpfs.dtsi` file are: * 1x SiFive E51 (RV32) * 4x SiFive U54 (RV64) Signed-off-by: Filip Kokosinski <[email protected]>
windowxia · Jan 31, 2024 · b5859ec · b5859ec
1 parent a3a4bf9
commit b5859ec
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Showing 2 changed files with 14 additions and 5 deletions.
diff --git a/dts/bindings/cpu/sifive,u54.yaml b/dts/bindings/cpu/sifive,u54.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive U54 Standard Core CPU
+
+compatible: "sifive,u54"
+
+include: sifive-common.yaml
diff --git a/dts/riscv/microchip/mpfs.dtsi b/dts/riscv/microchip/mpfs.dtsi
@@ -16,7 +16,7 @@
 		#size-cells = <0>;
 		cpu@0 {
 			clock-frequency = <0>;
-			compatible = "riscv";
+			compatible = "sifive,e51", "riscv";
 			device_type = "cpu";
 			reg = < 0x0 >;
 			riscv,isa = "rv64imac_zicsr_zifencei";
@@ -30,7 +30,7 @@
 
 		cpu@1 {
 			clock-frequency = <0>;
-			compatible = "riscv";
+			compatible = "sifive,u54", "riscv";
 			device_type = "cpu";
 			reg = < 0x1 >;
 			riscv,isa = "rv64gc";
@@ -44,7 +44,7 @@
 
 		cpu@2 {
 			clock-frequency = <0>;
-			compatible = "riscv";
+			compatible = "sifive,u54", "riscv";
 			device_type = "cpu";
 			reg = < 0x2 >;
 			riscv,isa = "rv64gc";
@@ -58,7 +58,7 @@
 
 		cpu@3 {
 			clock-frequency = <0>;
-			compatible = "riscv";
+			compatible = "sifive,u54", "riscv";
 			device_type = "cpu";
 			reg = < 0x3 >;
 			riscv,isa = "rv64gc";
@@ -72,7 +72,7 @@
 
 		cpu@4 {
 			clock-frequency = <0>;
-			compatible = "riscv";
+			compatible = "sifive,u54", "riscv";
 			device_type = "cpu";
 			reg = < 0x4 >;
 			riscv,isa = "rv64gc";