Update README.md

README.md

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 # Verilog-Practice
 
-[![996.icu](https://img.shields.io/badge/link-996.icu-red.svg)](https://996.icu) ![visitors](https://visitor-badge.glitch.me/badge?page_id=xiaopi-verilog-practice)
+[![996.icu](https://img.shields.io/badge/link-996.icu-red.svg)](https://996.icu) ![visitors](https://visitor-badge.glitch.me/badge?page_id=xiaopi-verilog-practice) <img alt="GitHub stars" src="https://img.shields.io/github/stars/xiaop1/Verilog-Practice" />
 
 There are some [HDLBits website][1] practices. And all of them have been verified. I really hope that my practices can help you to realize how Verilog works.
 
@@ -12,3 +12,7 @@ At the end, life is fantastic bro.
 
 [1]: https://hdlbits.01xz.net/wiki/Main_Page
 [2]: https://blog.began.me
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+## Star History
+
+[![Star History Chart](https://api.star-history.com/svg?repos=xiaop1/Verilog-Practice&type=Date)](https://star-history.com/#xiaop1/Verilog-Practice&Date)