xlsynth Verilog Style Guides

IMPORTANT: Originally forked from https://github.com/lowrisc/style-guides with our own changes applied on top. We will attempt to keep the style guide as close to lowRISC as possible, and may consider offering changes to upstream. Refer to the CHANGELOG and PR history to inspect where we have diverged from lowRISC.

This repository contains style guides curated by xlsynth for use in our code and documentation.

• SystemVerilog style guide
• Coding Style Guide for Design Verification

We invite issues and pull requests to add clarity to these guides.

All documents in this repository are licensed under Creative Commons Attribution 4.0 International (CC-BY 4.0).