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Merge pull request coolsnowwolf#537 from mcucore/master
add TP-Link WR941N V7 support
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target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941n-v7.c
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/* | ||
* TP-LINK TL-WR941N v7 board support | ||
* | ||
* Copyright (C) 2012 Gabor Juhos <[email protected]> | ||
* Copyright (C) 2014 Weijie Gao <[email protected]> | ||
* Copyright (c) 2018 Bin Chen <[email protected]> | ||
* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms of the GNU General Public License version 2 as published | ||
* by the Free Software Foundation. | ||
*/ | ||
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#include <linux/delay.h> | ||
#include <linux/pci.h> | ||
#include <linux/phy.h> | ||
#include <linux/gpio.h> | ||
#include <linux/platform_device.h> | ||
#include <linux/ath9k_platform.h> | ||
#include <linux/ar8216_platform.h> | ||
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#include <asm/mach-ath79/ar71xx_regs.h> | ||
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#include "common.h" | ||
#include "dev-ap9x-pci.h" | ||
#include "dev-eth.h" | ||
#include "dev-gpio-buttons.h" | ||
#include "dev-leds-gpio.h" | ||
#include "dev-m25p80.h" | ||
#include "dev-spi.h" | ||
/* #include "dev-usb.h" */ | ||
#include "dev-wmac.h" | ||
#include "machtypes.h" | ||
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#define WR941NV7_GPIO_LED_WLAN 12 | ||
#define WR941NV7_GPIO_LED_SYSTEM 19 | ||
#define WR941NV7_GPIO_LED_QSS 15 | ||
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#define WR941NV7_GPIO_BTN_RESET 16 | ||
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#define WR941NV7_KEYS_POLL_INTERVAL 20 /* msecs */ | ||
#define WR941NV7_KEYS_DEBOUNCE_INTERVAL (3 * WR941NV7_KEYS_POLL_INTERVAL) | ||
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#define ATH_MII_MGMT_CMD 0x24 | ||
#define ATH_MGMT_CMD_READ 0x1 | ||
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#define ATH_MII_MGMT_ADDRESS 0x28 | ||
#define ATH_ADDR_SHIFT 8 | ||
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#define ATH_MII_MGMT_CTRL 0x2c | ||
#define ATH_MII_MGMT_STATUS 0x30 | ||
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#define ATH_MII_MGMT_IND 0x34 | ||
#define ATH_MGMT_IND_BUSY (1 << 0) | ||
#define ATH_MGMT_IND_INVALID (1 << 2) | ||
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static const char *wr941nv7_part_probes[] = { | ||
"tp-link", | ||
NULL, | ||
}; | ||
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static struct flash_platform_data wr941nv7_flash_data = { | ||
.part_probes = wr941nv7_part_probes, | ||
}; | ||
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static struct gpio_led wr941nv7_leds_gpio[] __initdata = { | ||
{ | ||
.name = "tp-link:green:qss", | ||
.gpio = WR941NV7_GPIO_LED_QSS, | ||
.active_low = 1, | ||
}, | ||
{ | ||
.name = "tp-link:green:system", | ||
.gpio = WR941NV7_GPIO_LED_SYSTEM, | ||
.active_low = 1, | ||
}, | ||
{ | ||
.name = "tp-link:green:wlan", | ||
.gpio = WR941NV7_GPIO_LED_WLAN, | ||
.active_low = 1, | ||
}, | ||
}; | ||
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static struct gpio_keys_button wr941nv7_gpio_keys[] __initdata = { | ||
{ | ||
.desc = "reset", | ||
.type = EV_KEY, | ||
.code = KEY_RESTART, | ||
.debounce_interval = WR941NV7_KEYS_DEBOUNCE_INTERVAL, | ||
.gpio = WR941NV7_GPIO_BTN_RESET, | ||
.active_low = 1, | ||
}, | ||
}; | ||
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static struct mdio_board_info wr941nv7_mdio0_info[] = { | ||
{ | ||
.bus_id = "ag71xx-mdio.0", | ||
.phy_addr = 0, | ||
.platform_data = NULL, | ||
}, | ||
}; | ||
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static unsigned long __init ath_gmac_reg_rd(unsigned long reg) | ||
{ | ||
void __iomem *base; | ||
unsigned long t; | ||
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base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE); | ||
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t = __raw_readl(base + reg); | ||
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iounmap(base); | ||
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return t; | ||
} | ||
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static void __init ath_gmac_reg_wr(unsigned long reg, unsigned long value) | ||
{ | ||
void __iomem *base; | ||
unsigned long t = value; | ||
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base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE); | ||
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__raw_writel(t, base + reg); | ||
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iounmap(base); | ||
} | ||
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static void __init phy_reg_write(unsigned char phy_addr, unsigned char reg, unsigned short data) | ||
{ | ||
unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg; | ||
volatile int rddata; | ||
unsigned short ii = 0xFFFF; | ||
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do | ||
{ | ||
udelay(5); | ||
rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1; | ||
} while (rddata && --ii); | ||
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ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr); | ||
ath_gmac_reg_wr(ATH_MII_MGMT_CTRL, data); | ||
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do | ||
{ | ||
udelay(5); | ||
rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1; | ||
} while (rddata && --ii); | ||
} | ||
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static unsigned short __init phy_reg_read(unsigned char phy_addr, unsigned char reg) | ||
{ | ||
unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg, val; | ||
volatile int rddata; | ||
unsigned short ii = 0xffff; | ||
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do | ||
{ | ||
udelay(5); | ||
rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1; | ||
} while (rddata && --ii); | ||
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ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0); | ||
ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr); | ||
ath_gmac_reg_wr(ATH_MII_MGMT_CMD, ATH_MGMT_CMD_READ); | ||
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do | ||
{ | ||
udelay(5); | ||
rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1; | ||
} while (rddata && --ii); | ||
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val = ath_gmac_reg_rd(ATH_MII_MGMT_STATUS); | ||
ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0); | ||
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return val; | ||
} | ||
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static void __init athrs27_reg_write(unsigned int s27_addr, unsigned int s27_write_data) | ||
{ | ||
unsigned int addr_temp; | ||
unsigned int data; | ||
unsigned char phy_address, reg_address; | ||
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addr_temp = (s27_addr) >> 2; | ||
data = addr_temp >> 7; | ||
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phy_address = 0x1f; | ||
reg_address = 0x10; | ||
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phy_reg_write(phy_address, reg_address, data); | ||
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phy_address = (0x17 & ((addr_temp >> 4) | 0x10)); | ||
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reg_address = (((addr_temp << 1) & 0x1e) | 0x1); | ||
data = (s27_write_data >> 16) & 0xffff; | ||
phy_reg_write(phy_address, reg_address, data); | ||
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reg_address = ((addr_temp << 1) & 0x1e); | ||
data = s27_write_data & 0xffff; | ||
phy_reg_write(phy_address, reg_address, data); | ||
} | ||
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static unsigned int __init athrs27_reg_read(unsigned int s27_addr) | ||
{ | ||
unsigned int addr_temp; | ||
unsigned int s27_rd_csr_low, s27_rd_csr_high, s27_rd_csr; | ||
unsigned int data; | ||
unsigned char phy_address, reg_address; | ||
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addr_temp = s27_addr >>2; | ||
data = addr_temp >> 7; | ||
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phy_address = 0x1f; | ||
reg_address = 0x10; | ||
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phy_reg_write(phy_address, reg_address, data); | ||
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phy_address = (0x17 & ((addr_temp >> 4) | 0x10)); | ||
reg_address = ((addr_temp << 1) & 0x1e); | ||
s27_rd_csr_low = (unsigned int) phy_reg_read(phy_address, reg_address); | ||
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reg_address = reg_address | 0x1; | ||
s27_rd_csr_high = (unsigned int) phy_reg_read(phy_address, reg_address); | ||
s27_rd_csr = (s27_rd_csr_high << 16) | s27_rd_csr_low ; | ||
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return (s27_rd_csr); | ||
} | ||
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static void __init ar8236_reset(void) | ||
{ | ||
unsigned short i = 60; | ||
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athrs27_reg_write(0x0, athrs27_reg_read(0x0) | 0x80000000); | ||
while (i--) | ||
{ | ||
mdelay(100); | ||
if (!(athrs27_reg_read(0x0) & 0x80000000)) | ||
break; | ||
} | ||
} | ||
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static void __init wr941nv7_setup(void) | ||
{ | ||
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); | ||
u8 *art = (u8 *) KSEG1ADDR(0x1fff1000); | ||
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ath79_register_m25p80(&wr941nv7_flash_data); | ||
ath79_register_leds_gpio(-1, ARRAY_SIZE(wr941nv7_leds_gpio), | ||
wr941nv7_leds_gpio); | ||
ath79_register_gpio_keys_polled(-1, WR941NV7_KEYS_POLL_INTERVAL, | ||
ARRAY_SIZE(wr941nv7_gpio_keys), | ||
wr941nv7_gpio_keys); | ||
/* WiFi Port */ | ||
ath79_register_wmac(art, mac); | ||
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ar8236_reset(); | ||
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_MII_GE0 | | ||
QCA955X_ETH_CFG_MII_GE0_SLAVE); | ||
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mdiobus_register_board_info(wr941nv7_mdio0_info, | ||
ARRAY_SIZE(wr941nv7_mdio0_info)); | ||
ath79_register_mdio(0, 0x0); | ||
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/* WAN Port */ | ||
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); | ||
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/* GMAC0 is connected to an AR8236 switch */ | ||
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; | ||
ath79_eth0_data.speed = SPEED_100; | ||
ath79_eth0_data.duplex = DUPLEX_FULL; | ||
ath79_eth0_data.phy_mask = BIT(0); | ||
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; | ||
ath79_register_eth(0); | ||
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/* ath79_register_usb(); */ | ||
} | ||
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MIPS_MACHINE(ATH79_MACH_TL_WR941N_V7, "TL-WR941N-v7", | ||
"TP-LINK TL-WR941N v7", | ||
wr941nv7_setup); |
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