🏠 MEGA: Memory-Efficient 4D Gaussian Splatting for Dynamic Scenes

A minimal GPU design in Verilog to learn how GPUs work from the ground up

mnist_trained_model with torch

[ICLR 2025] DuoAttention: Efficient Long-Context LLM Inference with Retrieval and Streaming Heads

Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。

Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

A tool to modify ONNX models in a visualization fashion, based on Netron and Flask.

Dataflow compiler for QNN inference on FPGAs

Open source machine learning accelerators

xkDLA：XinKai Deep Learning Accelerator (RTL)

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

Run LeNet-5 baremetal

An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.

Sparse CNN Accelerator targeting Intel FPGA

General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。

基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现

Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.

Reconfigurable implementation and evaluation of the Bit Pragmatic Deep Learning Inference engine

XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.

[TECS'23] A project on the co-design of Accelerators and CNNs.

FPGA accelerated TinyYOLO v2 object detection neural network

This is a repo for my research on reconfigureable hardware