Business Demo for CloudWeGo

A Matlab implementation of Reed Solomen (RS code) for any length and gf order 任意长度和有限域阶数的里德所罗门码MATLAB实现

Verilog model for Fractional Sample Rate Converter

The best rtl_uart in github! This is a UART design based on AXI Stream/Ready Vallid protocol. Support parameterized data bit width, clock frequency, baud rate, and parity check.

Nemu PA——给个Star？【仅供交流学习使用，未经许可禁止传播！】(PA3有个地方取地址时存在左移右移问题，在PA4更改这个bug了，请注意！)

抄nemu的同学点个star好嘛