GitHub - yujulucy/EE2020_FPGA_project: Verilog codes for my EE2020 FPGA Project (AY15/16)

yujulucy / EE2020_FPGA_project Public

forked from tlautrec/EE2020_FPGA_project

Verilog codes for my EE2020 FPGA Project (AY15/16)

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
project.cache/wt		project.cache/wt
project.hw		project.hw
project.runs		project.runs
project.sim/sim_1/behav		project.sim/sim_1/behav
project.srcs		project.srcs
..hdi.isWriteableTest.4328.tmp		..hdi.isWriteableTest.4328.tmp
..hdi.isWriteableTest.5020.tmp		..hdi.isWriteableTest.5020.tmp
hs_err_pid4328.dmp		hs_err_pid4328.dmp
hs_err_pid4328.log		hs_err_pid4328.log
hs_err_pid5020.log		hs_err_pid5020.log
project.xpr		project.xpr
vivado.jou		vivado.jou
vivado.log		vivado.log
vivado_4328.backup.jou		vivado_4328.backup.jou
vivado_4328.backup.log		vivado_4328.backup.log
vivado_4488.backup.jou		vivado_4488.backup.jou
vivado_4488.backup.log		vivado_4488.backup.log
vivado_5020.backup.jou		vivado_5020.backup.jou
vivado_5020.backup.log		vivado_5020.backup.log
vivado_9260.backup.jou		vivado_9260.backup.jou
vivado_9260.backup.log		vivado_9260.backup.log
vivado_pid4328.str		vivado_pid4328.str
vivado_pid5020.str		vivado_pid5020.str
webtalk.jou		webtalk.jou
webtalk.log		webtalk.log