Implement SPI deinit

zacck · Nov 7, 2023 · 2931098 · 2931098
1 parent 9c52a50
commit 2931098
Show file tree

Hide file tree

Showing 2 changed files with 48 additions and 42 deletions.
diff --git a/drivers/Inc/stm32f407xx.h b/drivers/Inc/stm32f407xx.h
@@ -286,7 +286,7 @@ typedef struct
 #define SPI1_REG_RESET()	do {(RCC->APB2RSTR |= (1 << 12)); (RCC->AHB1RSTR &= ~(1 << 0));} while (0)
 #define SPI2_REG_RESET()	do {(RCC->APB1RSTR |= (1 << 14)); (RCC->AHB1RSTR &= ~(1 << 0));} while (0)
 #define SPI3_REG_RESET()	do {(RCC->APB1RSTR |= (1 << 15)); (RCC->AHB1RSTR &= ~(1 << 0));} while (0)
-#define SPI4_REG_RESET()	do {(RCC->APB2RSTR |= (1 << 13); (RCC->AHB1RSTR &= ~(1 << 0));} while (0)
+#define SPI4_REG_RESET()	do {(RCC->APB2RSTR |= (1 << 13)); (RCC->AHB1RSTR &= ~(1 << 0));} while (0)
 
 //returns the port code given the base address
 #define GPIO_BASEADDR_TO_CODE(x) ((x == GPIOA) ? 0: \

diff --git a/drivers/src/stm32f407xx_spi.c b/drivers/src/stm32f407xx_spi.c
@@ -1,4 +1,4 @@
- /*
+/*
  * stm32f407xx_spi.c
  *
  *  Created on: Nov 1, 2023
@@ -18,33 +18,31 @@
  * @return void
  * @note
  *  */
-void SPI_PCLK_CTRL(SPI_RegDef_t *pSPIx, uint8_t EnorDi){
+void SPI_PCLK_CTRL(SPI_RegDef_t *pSPIx, uint8_t EnorDi) {
 	if (EnorDi == ENABLE) {
-			if (pSPIx == SPI1) {
-				SPI1_PCLK_EN();
-			} else if (pSPIx == SPI2) {
-				SPI2_PCLK_EN();
-			} else if (pSPIx == SPI3) {
-				SPI3_PCLK_EN();
-			} else if (pSPIx == SPI4) {
-				SPI4_PCLK_EN();
-			}
-		} else {
-			if (pSPIx == SPI1) {
-				SPI1_PCLK_DI();
-			} else if (pSPIx == SPI2) {
-				SPI2_PCLK_DI();
-			} else if (pSPIx == SPI3) {
-				SPI3_PCLK_DI();
-			} else if (pSPIx == SPI4) {
-				SPI4_PCLK_DI();
-			}
-
+		if (pSPIx == SPI1) {
+			SPI1_PCLK_EN();
+		} else if (pSPIx == SPI2) {
+			SPI2_PCLK_EN();
+		} else if (pSPIx == SPI3) {
+			SPI3_PCLK_EN();
+		} else if (pSPIx == SPI4) {
+			SPI4_PCLK_EN();
+		}
+	} else {
+		if (pSPIx == SPI1) {
+			SPI1_PCLK_DI();
+		} else if (pSPIx == SPI2) {
+			SPI2_PCLK_DI();
+		} else if (pSPIx == SPI3) {
+			SPI3_PCLK_DI();
+		} else if (pSPIx == SPI4) {
+			SPI4_PCLK_DI();
 		}
 
-}
-
+	}
 
+}
 
 /******
  * @fn SPI_Init
@@ -57,45 +55,53 @@ void SPI_PCLK_CTRL(SPI_RegDef_t *pSPIx, uint8_t EnorDi){
  * @note
  *  */
 
-void SPI_Init(SPI_Handle_t *pSPIHandle){
+void SPI_Init(SPI_Handle_t *pSPIHandle) {
 	//configure CR1
-	uint32_t  tempreg  = 0;
+	uint32_t tempreg = 0;
 
 	//device mode
 	tempreg |= pSPIHandle->SPIConfig.SPI_DeviceMode << SPI_CR1_MSTR;
 
 	//bus config
-	if(pSPIHandle->SPIConfig.SPI_BUSConfig == SPI_BUS_CONFIG_FD){
+	if (pSPIHandle->SPIConfig.SPI_BUSConfig == SPI_BUS_CONFIG_FD) {
 		//clear bidimode
-		tempreg &= ~(1<< SPI_CR1_MSTR);
-	} else if(pSPIHandle->SPIConfig.SPI_BUSConfig == SPI_BUS_CONFIG_HD){
+		tempreg &= ~(1 << SPI_CR1_MSTR);
+	} else if (pSPIHandle->SPIConfig.SPI_BUSConfig == SPI_BUS_CONFIG_HD) {
 		//set bidi mode
-		tempreg |= (1<< SPI_CR1_MSTR);
+		tempreg |= (1 << SPI_CR1_MSTR);
 
-	} else if(pSPIHandle->SPIConfig.SPI_BUSConfig == SPI_BUS_CONFIG_SIMPLEX_RXONLY){
+	} else if (pSPIHandle->SPIConfig.SPI_BUSConfig
+			== SPI_BUS_CONFIG_SIMPLEX_RXONLY) {
 		//clear bidi
-		tempreg &= ~(1<< SPI_CR1_MSTR);
+		tempreg &= ~(1 << SPI_CR1_MSTR);
 		//set rxonly
-		tempreg |= (1<< SPI_CR1_RXONLY);
+		tempreg |= (1 << SPI_CR1_RXONLY);
 
 	}
 
 	//configure clock
-	tempreg  |= pSPIHandle->SPIConfig.SPI_SclkSpeed << SPI_CR1_BR;
+	tempreg |= pSPIHandle->SPIConfig.SPI_SclkSpeed << SPI_CR1_BR;
 
 	// cofigure frame size
-	tempreg  |= pSPIHandle->SPIConfig.SPI_DFF << SPI_CR1_DFF;
+	tempreg |= pSPIHandle->SPIConfig.SPI_DFF << SPI_CR1_DFF;
 
 	//cpol
-	tempreg  |= pSPIHandle->SPIConfig.SPI_CPOL << SPI_CR1_CPOL;
+	tempreg |= pSPIHandle->SPIConfig.SPI_CPOL << SPI_CR1_CPOL;
 
 	//CPHA
-	tempreg  |= pSPIHandle->SPIConfig.SPI_CPHA << SPI_CR1_CPHA;
-
-
-
-
+	tempreg |= pSPIHandle->SPIConfig.SPI_CPHA << SPI_CR1_CPHA;
 
+}
 
+void SPI_DeInit(SPI_RegDef_t *pSPIx) {
+	if (pSPIx == SPI1) {
+		SPI1_REG_RESET();
+	} else if (pSPIx == SPI2) {
+		SPI2_REG_RESET();
+	} else if (pSPIx == SPI3) {
+		SPI3_REG_RESET();
+	} else if (pSPIx == SPI4) {
+		SPI4_REG_RESET();
+	}
 }