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  1. Trigger Trigger Public

    Forked from yuhanzhu612/Trigger

    RISC-V core designed by zyh in chisel language

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  2. oscpu-chisel-framework oscpu-chisel-framework Public

    Forked from fangjiangff/oscpu-chisel-framework

    Chisel development framework for OSCPU project

    Scala

  3. oscpu-framework oscpu-framework Public

    Forked from TeletubbyZJC/oscpu-framework

    oscpu-framework

    Verilog

  4. XiangShan XiangShan Public

    Forked from OpenXiangShan/XiangShan

    Open-source high-performance RISC-V processor

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  5. SHA_SM3_SM4-Encryption-Algorithm SHA_SM3_SM4-Encryption-Algorithm Public

    Forked from RicoLi424/SHA_SM3_SM4-Encryption-Algorithm

    With basic SM3 & SM4 Encryption IP implemented with both Verilog and C , along with package for switching between SHA and SM3

    C

  6. SM4-SBOX SM4-SBOX Public

    Forked from raymondrc/SM4-SBOX

    Verilog Implementation of SM4 s-box

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