Skip to content

Commit

Permalink
Add files via upload
Browse files Browse the repository at this point in the history
  • Loading branch information
Dennis-Chhun authored Jan 19, 2017
1 parent d150c93 commit b5f279b
Show file tree
Hide file tree
Showing 3 changed files with 571 additions and 0 deletions.
88 changes: 88 additions & 0 deletions src/ScoreDecoder.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,88 @@
module ScoreDecoder(in, Hex2, Hex1);
input [4:0]in;
output reg [6:0] Hex2,Hex1;

parameter zero = 7'b1000000;
parameter one = 7'b1111001;
parameter two = 7'b0100100;
parameter three = 7'b0110000;
parameter four = 7'b0011001;
parameter five = 7'b0010010;
parameter six = 7'b0000010;
parameter seven = 7'b1111000;
parameter eight = 7'b0000000;
parameter nine = 7'b0011000;

parameter blank = 7'b1111111;

always@(*) begin
case(in)
0: begin
Hex1 <= zero;
Hex2 <= blank;
end
1: begin
Hex1 <= one;
Hex2 <= blank;
end
2: begin
Hex1 <= two;
Hex2 <= blank;
end
3: begin
Hex1 <= three;
Hex2 <= blank;
end
4: begin
Hex1 <= four;
Hex2 <= blank;
end
5: begin
Hex1 <= five;
Hex2 <= blank;
end
6: begin
Hex1 <= six;
Hex2 <= blank;
end
7: begin
Hex1 <= seven;
Hex2 <= blank;
end
8: begin
Hex1 <= eight;
Hex2 <= blank;
end
9: begin
Hex1 <= nine;
Hex2 <= blank;
end
10: begin
Hex1 <= zero;
Hex2 <= one;
end
11: begin
Hex1 <= one;
Hex2 <= one;
end
12: begin
Hex1 <= two;
Hex2 <= one;
end
13: begin
Hex1 <= three;
Hex2 <= one;
end
14: begin
Hex1 <= four;
Hex2 <= one;
end
15: begin
Hex1 <= five;
Hex2 <= one;
end
endcase
end

endmodule

113 changes: 113 additions & 0 deletions src/VGAController.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,113 @@
// This is a controller written for a VGA Monitor with resolution 1280 by 1024 with an refresh rate of 60 fps
// VGA Controller use to generate signals for the monitor
module VGAController (PixelClock,
inRed,
inGreen,
inBlue,
outRed,
outGreen,
outBlue,
VertSynchOut,
HorSynchOut,
XPosition,
YPosition);
//=======================================================
// Parameter Declarations
//=======================================================
// Parameters are set for a 1280 by 1024 pixel monitor running at 60 frames per second
// X Screen Constants
parameter XLimit = 1688;
parameter XVisible = 1280;
parameter XSynchPulse = 112;
parameter XBackPorch = 248;
// Y Screen Constants
parameter YLimit = 1066;
parameter YVisible = 1024;
parameter YSynchPulse = 3;
parameter YBackPorch = 38;

//=======================================================
// Port Declarations
//=======================================================
input PixelClock;
input [7:0] inRed;
input [7:0] inGreen;
input [7:0] inBlue;
output [7:0] outRed;
output [7:0] outGreen;
output [7:0] outBlue;
output VertSynchOut;
output HorSynchOut;
output [10:0] XPosition;
output [10:0] YPosition;

//========================================================
// REG/WIRE declarations
//========================================================

reg [10:0] XTiming;
reg [10:0] YTiming;
reg HorSynch;
reg VertSynch;

//========================================================
// Structural coding
//========================================================
assign XPosition = XTiming - (XSynchPulse + XBackPorch);
assign YPosition = YTiming - (YSynchPulse + YBackPorch);


always@(posedge PixelClock)// Control X Timing
begin
if (XTiming >= XLimit)
XTiming <= 11'd0;
else
XTiming <= XTiming + 1;
end

always@(posedge PixelClock)// Control Y Timing
begin
if (YTiming >= YLimit && XTiming >= XLimit)
YTiming <= 11'd0;
else if (XTiming >= XLimit && YTiming < YLimit)
YTiming <= YTiming + 1;
else
YTiming <= YTiming;
end

always@(posedge PixelClock)// Control Vertical Synch Signal
begin
if (YTiming >= 0 && YTiming < YSynchPulse)
VertSynch <= 1'b0;
else
VertSynch <= 1'b1;
end

always@(posedge PixelClock)// Control Horizontal Synch Signal
begin
if (XTiming >= 0 && XTiming < XSynchPulse)
HorSynch <= 1'b0;
else
HorSynch <= 1'b1;
end

// Draw black in off screen areas of screen
assign outRed = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inRed : 8'b0;
assign outGreen = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inGreen : 8'b0;
assign outBlue = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inBlue : 8'b0;

assign VertSynchOut = VertSynch;
assign HorSynchOut = HorSynch;


// Initialization registers block
initial
begin
XTiming = 11'b0;
YTiming = 11'b0;
HorSynch = 1'b1;
VertSynch = 1'b1;
end


endmodule
Loading

0 comments on commit b5f279b

Please sign in to comment.