EDANexus
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OpenDB
OpenDB PublicForked from The-OpenROAD-Project/OpenDB
Database and Tool Framework for EDA
C++ 1
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yosys_gatemap
yosys_gatemap PublicForked from tomverbeure/yosys_gatemap
An example that shows how to map a design to a custom cell library.
Verilog
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yosys_split_ops
yosys_split_ops PublicForked from tomverbeure/yosys_split_ops
Yosys techmaps to split operations on large vectors into multiple smaller ones.
Verilog
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yosys_techmap_blog
yosys_techmap_blog PublicForked from tomverbeure/yosys_techmap_blog
Example repo for blog post
Verilog
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Repositories
- PyRTL Public Forked from UCSBarchlab/PyRTL
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
EDANexus/PyRTL’s past year of commit activity - IIC-OSIC-TOOLS Public Forked from iic-jku/IIC-OSIC-TOOLS
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
EDANexus/IIC-OSIC-TOOLS’s past year of commit activity
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