EDANexus
Popular repositories Loading
-
OpenDB
OpenDB PublicForked from The-OpenROAD-Project/OpenDB
Database and Tool Framework for EDA
C++ 1
-
-
yosys_gatemap
yosys_gatemap PublicForked from tomverbeure/yosys_gatemap
An example that shows how to map a design to a custom cell library.
Verilog
-
yosys_split_ops
yosys_split_ops PublicForked from tomverbeure/yosys_split_ops
Yosys techmaps to split operations on large vectors into multiple smaller ones.
Verilog
-
yosys_techmap_blog
yosys_techmap_blog PublicForked from tomverbeure/yosys_techmap_blog
Example repo for blog post
Verilog
-
Repositories
- PyRTL Public Forked from UCSBarchlab/PyRTL
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
EDANexus/PyRTL’s past year of commit activity - atopile Public Forked from atopile/atopile
Design circuit boards with code! ✨ Get software-like design reuse 🚀, validation, version control and collaboration in hardware; starting with electronics ⚡️
EDANexus/atopile’s past year of commit activity - oss-cad-suite-build Public Forked from YosysHQ/oss-cad-suite-build
Multi-platform nightly builds of open source digital design and verification tools
EDANexus/oss-cad-suite-build’s past year of commit activity - naja Public Forked from najaeda/naja
Structural Netlist API (and more) for EDA post synthesis flow development
EDANexus/naja’s past year of commit activity - pycaliper Public Forked from IntelLabs/pycaliper
PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g., Verilog, SystemVerilog)
EDANexus/pycaliper’s past year of commit activity
People
This organization has no public members. You must be a member to see who’s a part of this organization.
Top languages
Loading…
Most used topics
Loading…