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Geek3600
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
4 stage, in-order, secure RISC-V core based on the CV32E40P
