🤗 Transformers: State-of-the-art Machine Learning for Pytorch, TensorFlow, and JAX.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Transformer: PyTorch Implementation of "Attention Is All You Need"

本人的科研经验

Simple RISC-V 3-stage Pipeline in Chisel

A visual no-code/code-free web crawler/spider易采集：一个可视化浏览器自动化测试/数据采集/爬虫软件，可以无代码图形化的设计和执行爬虫任务。别名：ServiceWrapper面向Web应用的智能化服务封装系统。

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The…

RiscV CPU implementation in Amaranth HDL (aka nMigen)

Yosys Open SYnthesis Suite

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Collect some CS textbooks for learning.

Verilog AXI components for FPGA implementation

The Ultra-Low Power RISC-V Core

Linux 101 学生课程教材与讲义

OpenXuantie - OpenC910 Core

the CS missing semester Chinese version

Collect some IC textbooks for learning.

OpenXuantie - OpenE902 Core

OpenXuantie - OpenE906 Core

OpenXuantie - OpenC906 Core

Open Source Chip Project by University (OSCPU) - Zhoushan Core

RISC-V Processor written in Amaranth HDL

IC design and development should be faster，simpler and more reliable

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2