Hardware Description Languages

Open, Modular, Deep Learning Accelerator

Working draft of the proposed RISC-V V vector extension

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

Open-source high-performance RISC-V processor

[ICML'21 Oral] I-BERT: Integer-only BERT Quantization

🤗 Transformers: State-of-the-art Machine Learning for Pytorch, TensorFlow, and JAX.

Transformer: PyTorch Implementation of "Attention Is All You Need"

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

本人的科研经验

A visual no-code/code-free web crawler/spider易采集：一个可视化浏览器自动化测试/数据采集/爬虫软件，可以无代码图形化的设计和执行爬虫任务。别名：ServiceWrapper面向Web应用的智能化服务封装系统。

PLCT实验室的公开演讲，或者决定公开的组内报告

automatic-verilog based on vimscript

All in one vscode plugin for HDL development

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Lab specs for asic-labs-sp23 is organized here!

RISC-V Tools (ISA Simulator and Tests)

The official repository for the gem5 computer-system architecture simulator.

Yosys Open SYnthesis Suite

Collect some IC textbooks for learning.

Collect some CS textbooks for learning.