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Commits on Oct 4, 2022

• [formal] Remove build infrastructure for instruction cache assertions

  marnovandermaas

  committed
  1cdd403

• [formal] Remove build infrastructure for data independent timing

  marnovandermaas

  committed
  ab350c4

• [riscv-formal] Removing unsupported and broken feature

  marnovandermaas

  committed
  fce41ff

• [formal] Added missing prim secded package

  marnovandermaas

  committed
  43dc5e8

Commits on Oct 16, 2021

• Change use of blocking assignment to non-blocking inside always_ff

  Show description for a345da3
  

  hzeller

  authored and

  rswarbrick

  committed
  a345da3

Commits on Jul 14, 2021

• [formal] Read Verilog files in Yosys

  Show description for 7032df0
  

  towoe

  authored and

  rswarbrick

  committed
  7032df0

• [formal] Switch to new top level

  Show description for e1eaa1c
  

  towoe

  authored and

  rswarbrick

  committed
  e1eaa1c

• Get riscv-formal flow working again

  Show description for 594c236
  rswarbrick

  committed
  594c236

Commits on Jun 15, 2021

• [dv] Fix icache formal tb after recent parameter changes

  rswarbrick

  committed
  6c44070

Commits on Dec 2, 2020

• [rtl] Add branch prediction signals to icache

  Show description for 8db89a9
  

  Tom Roberts

  authored and

  tomeroberts

  committed
  8db89a9

• [rtl] icache performance updates

  Show description for 64ee9a9
  

  Tom Roberts

  authored and

  tomeroberts

  committed
  64ee9a9

• [fpv] Assume icache req_i input is low when in reset

  Show description for 38a6b59
  

  rswarbrick

  authored and

  tomeroberts

  committed
  38a6b59

Commits on Sep 16, 2020

• [formal] Add check for multdiv cycle consumption

  Show description for 1553636
  

  towoe

  authored and

  rswarbrick

  committed
  1553636

• Move sv2v script into standalone core file

  Show description for c8d4f2d
  

  towoe

  authored and

  rswarbrick

  committed
  c8d4f2d

Commits on Aug 31, 2020

• Port ICache formal core file to final Edalize design

  Show description for fb5d87b
  rswarbrick

  committed
  fb5d87b

Commits on Jul 2, 2020

• Add some formal cover properties for ICache

  Show description for fb2a17a
  rswarbrick

  committed
  fb2a17a

• Add an ICacheECC parameter to ICache formal flow

  Show description for 4a20bc4
  rswarbrick

  committed
  4a20bc4

• Formal protocol checking for icache <-> core interface

  Show description for 49c9113
  rswarbrick

  committed
  49c9113

• A simple formal flow for the ICache based on SymbiYosys

  Show description for ee1ca61
  rswarbrick

  committed
  ee1ca61

• Move riscv-formal code into formal/riscv-formal

  Show description for e4dbe46
  rswarbrick

  committed
  e4dbe46

Commits on Jun 8, 2020

• [syn] Update path to prim_assert

  Show description for 85ce387
  

  Tom Roberts

  authored and

  tomeroberts

  committed
  85ce387

• [rtl] Rewrite perf counters to be Yosys compatible

  Show description for 8332f7d
  

  Tom Roberts

  authored and

  tomeroberts

  committed
  8332f7d

Commits on May 25, 2020

• [formal] Create Ibex Verilog source

  Show description for 8779bcd
  

  towoe

  authored and

  imphil

  committed
  8779bcd

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