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Fix typo in readme
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Razer6 committed Oct 7, 2016
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# RI5CY: RISC-V Core

RI5CY is a small 4-stage RISC-V core. It starte its life as a
fork of the OR10N cpu core that is based on the OpenRISC ISA.
RI5CY is a small 4-stage RISC-V core. It started its life as a
fork of the OR10N CPU core that is based on the OpenRISC ISA.

RI5CY fully implements the RV32I instruction set, the multiply instruction from
RV32M and many custom instruction set extensions that improve its performance
Expand All @@ -19,4 +19,3 @@ in `docs/datasheet/`.
It is written using LaTeX and can be generated as follows

make all

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