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- Run out of SRAM, it goes quite a lot faster - Cache the DAP clock frequency - Read RDATA and write WDATA all in one go, and merge the turnaround into the ACK phase. Reduces the number of missed PIO SM cycles during an SWD transfer Also fix a compiler warning and demote the loglevel of some debug messages. Signed-off-by: Jonathan Bell <[email protected]>
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