Revenantx86
Follow
-
-
tiny-SAR Public
8-bit Succesive approximation register analog to digital converter (SAR-ADC)
Makefile UpdatedDec 20, 2024 -
comparator_sky130_cace Public
Cace Template for comparator Internal testing purpose
Tcl UpdatedDec 20, 2024 -
xschem Public
Forked from StefanSchippers/xschemA schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
C Other UpdatedNov 10, 2024 -
-
tt09-fifo-wdelay Public
tt09 based fifo with delay to create timing analysis template
Verilog Apache License 2.0 UpdatedOct 29, 2024 -
verilog_sta Public
static timing analysis using OpenSTA. Example scripts for using verilog, spice, parasitic timing analysis
Verilog UpdatedOct 29, 2024 -
tt09-TinyTPU-Reforged Public template
Forked from TinyTapeout/tt09-verilog-templateTiny-Tapeout-9, TinyTPU submission with timing report. Aim is to implement
Verilog Apache License 2.0 UpdatedOct 27, 2024 -
xschem_openlane_integration Public
Integration test for openlane, xschem, and cace
MIT License UpdatedOct 8, 2024 -
r2r-dac Public
Digital To Analog converter using r2r ladder formation
Verilog Apache License 2.0 UpdatedSep 11, 2024 -
-
tt07-tinytpu Public
TinyTPU module with only 1 Core and 2x2 matrix multiplication support !
-
ota_5t Public
5 Transistor Single ended operational amplifier design with fully open source tools.
Tcl Apache License 2.0 UpdatedSep 4, 2024 -
ota_5t_ring Public
ringed ota amplifier, created to compare the performance between ring isolated transistors vs not isolated
UpdatedSep 4, 2024 -
MOSFET_model Public
Forked from ACMmodel/MOSFET_modelA simple MOSFET model with only 5-DC-parameters for circuit simulation
Educational Community License v2.0 UpdatedJun 25, 2024 -
TinyDFU Public
Tiny DFU module with stm32 mcu, 9-DOF IMU, SD Card, and USB connection.
MIT License UpdatedJun 7, 2024 -
uart Public
new uart module with AXI compatibility and more features
Verilog MIT License UpdatedMay 18, 2024 -
-
tt06-XY_Controller Public template
Forked from CKPope/tt06-verilog-templateCKPope's tinytapeout chip. Credit to @CKPope
Verilog Apache License 2.0 UpdatedApr 15, 2024 -
-
-
-
-
-
-
VSDBabySoC Public
Forked from manili/VSDBabySoCVSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
Verilog Apache License 2.0 UpdatedJan 4, 2022