This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).

Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"

8 Bit CPU in Verilog created for TinyTapeout09, based on SAP-1 design with added Programmer Module

ASIC Silicon chip developed and created using the Tiny Tapeout software.

this repository will maintain simulation files and other relevant files on the SAR Logic circuitry worked on in VSD Online Internship 2020

A 10bit SAR ADC in Sky130

To make the IC simulation with Skywater 130 PDK, i created a script that install the tools to run the first simulation.

PLL Designs on Skywater 130nm MPW

A simple MOSFET model with only 5-DC-parameters for circuit simulation

12 bit SAR ADC IP in Skywater 130 nm PDK

This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

KLayout Main Sources

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

uart module verilog