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1. Dynamic-Pipeline-CPU Dynamic-Pipeline-CPU Public

   A simple dynamic pipeline CPU with 54 instructions based on MIPS architecture.

   Verilog 7

2. Static-Pipeline-CPU Static-Pipeline-CPU Public

   A simple static pipeline CPU with 54 instructions based on MIPS architecture.

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3. VGA-Verilog VGA-Verilog Public

   A simple VGA interface for FPGA written in verilog.

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4. gobang_AI gobang_AI Public

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   基于博弈树α-β剪枝搜索的五子棋AI

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5. Single-Cycle-CPU Single-Cycle-CPU Public

   A simple single cycle CPU with 31 instructions based on MIPS architecture.

   VHDL 1

6. Multi-Cycle-CPU Multi-Cycle-CPU Public

   A simple multi-cycle CPU with 54 instructions based on MIPS architecture.

   Verilog 1