A simple multi-cycle CPU with 54 instructions based on MIPS architecture.
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Programming Language:
Verilog HDL
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Development Board:
Xilinx NEXYS 4 DDR
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Design Tools:
Vivado 2018.2
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RobertRWu/Multi-Cycle-CPU
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A simple multi-cycle CPU with 54 instructions based on MIPS architecture.
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