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Machine: implemented RISC-V A extension for RV32IMA/RV64IMA support
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Signed-off-by: Pavel Pisa <[email protected]>
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@ppisa
ppisa committed Dec 7, 2023
1 parent fd95041 commit a2bc984
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Showing 10 changed files with 306 additions and 16 deletions.
8 changes: 4 additions & 4 deletions .github/workflows/debug.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -104,28 +104,28 @@ jobs:
if: matrix.config.os != 'ubuntu-18.04'
working-directory: ${{ github.workspace }}/tests/riscv-official
#run: python qtrvsim_tester.py --no-64 ${{ github.workspace }}/build/target/qtrvsim_cli
run: python qtrvsim_tester.py -M ${{ github.workspace }}/build/target/qtrvsim_cli
run: python qtrvsim_tester.py -M -A ${{ github.workspace }}/build/target/qtrvsim_cli

- name: Official RISC-V tests (pipelined)
# The testing python script does not support Ubuntu 18
if: matrix.config.os != 'ubuntu-18.04'
working-directory: ${{ github.workspace }}/tests/riscv-official
#run: python qtrvsim_tester.py --no-64 ${{ github.workspace }}/build/target/qtrvsim_cli
run: python qtrvsim_tester.py -M --pipeline ${{ github.workspace }}/build/target/qtrvsim_cli
run: python qtrvsim_tester.py -M -A --pipeline ${{ github.workspace }}/build/target/qtrvsim_cli

- name: Official RISC-V tests (single cycle, cached)
# The testing python script does not support Ubuntu 18
if: matrix.config.os != 'ubuntu-18.04'
working-directory: ${{ github.workspace }}/tests/riscv-official
#run: python qtrvsim_tester.py --no-64 ${{ github.workspace }}/build/target/qtrvsim_cli
run: python qtrvsim_tester.py -M --cache ${{ github.workspace }}/build/target/qtrvsim_cli
run: python qtrvsim_tester.py -M -A --cache ${{ github.workspace }}/build/target/qtrvsim_cli

- name: Official RISC-V tests (pipelined, cached)
# The testing python script does not support Ubuntu 18
if: matrix.config.os != 'ubuntu-18.04'
working-directory: ${{ github.workspace }}/tests/riscv-official
#run: python qtrvsim_tester.py --no-64 ${{ github.workspace }}/build/target/qtrvsim_cli
run: python qtrvsim_tester.py -M --pipeline --cache ${{ github.workspace }}/build/target/qtrvsim_cli
run: python qtrvsim_tester.py -M -A --pipeline --cache ${{ github.workspace }}/build/target/qtrvsim_cli

- name: Store created artifacts
uses: actions/upload-artifact@v2
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1 change: 1 addition & 0 deletions src/machine/CMakeLists.txt
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Expand Up @@ -39,6 +39,7 @@ set(machine_HEADERS
machineconfig.h
machinedefs.h
memory/address.h
memory/address_range.h
memory/backend/backend_memory.h
memory/backend/lcddisplay.h
memory/backend/memory.h
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86 changes: 79 additions & 7 deletions src/machine/core.cpp
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Expand Up @@ -159,6 +159,38 @@ bool Core::handle_exception(
return ret;
}

static int32_t amo32_operations(enum AccessControl memctl, int32_t a, int32_t b) {
switch(memctl) {
case AC_AMOSWAP32: return b;
case AC_AMOADD32: return a + b;
case AC_AMOXOR32: return a ^ b;
case AC_AMOAND32: return a & b;
case AC_AMOOR32: return a | b;
case AC_AMOMIN32: return a < b? a: b;
case AC_AMOMAX32: return a < b? b: a;
case AC_AMOMINU32: return (uint32_t)a < (uint32_t)b? a: b;
case AC_AMOMAXU32: return (uint32_t)a < (uint32_t)b? b: a;
default: break;
}
return 0;
}

static int64_t amo64_operations(enum AccessControl memctl, int64_t a, int64_t b) {
switch(memctl) {
case AC_AMOSWAP64: return b;
case AC_AMOADD64: return a + b;
case AC_AMOXOR64: return a ^ b;
case AC_AMOAND64: return a & b;
case AC_AMOOR64: return a | b;
case AC_AMOMIN64: return a < b? a: b;
case AC_AMOMAX64: return a < b? b: a;
case AC_AMOMINU64: return (uint64_t)a < (uint64_t)b? a: b;
case AC_AMOMAXU64: return (uint64_t)a < (uint64_t)b? b: a;
default: break;
}
return 0;
}

enum ExceptionCause Core::memory_special(
enum AccessControl memctl,
int mode,
Expand All @@ -174,15 +206,55 @@ enum ExceptionCause Core::memory_special(
mem_data->sync();
mem_program->sync();
break;
case AC_STORE_CONDITIONAL:
case AC_LR32:
if (!memread) { break; }
state.LoadReservedRange = AddressRange(mem_addr, mem_addr + 3);
towrite_val = (int32_t)(mem_data->read_u32(mem_addr));
break;
case AC_SC32:
if (!memwrite) { break; }
mem_data->write_u32(mem_addr, rt_value.as_u32());
towrite_val = 1;
if (state.LoadReservedRange.contains(AddressRange(mem_addr, mem_addr + 3))) {
mem_data->write_u32(mem_addr, rt_value.as_u32());
towrite_val = 0;
} else {
towrite_val = 1;
}
state.LoadReservedRange.reset();
break;
case AC_LOAD_LINKED:
case AC_LR64:
if (!memread) { break; }
towrite_val = mem_data->read_u32(mem_addr);
state.LoadReservedRange = AddressRange(mem_addr, mem_addr + 7);
towrite_val = mem_data->read_u64(mem_addr);
break;
case AC_SC64:
if (!memwrite) { break; }
if (state.LoadReservedRange.contains(AddressRange(mem_addr, mem_addr + 7))) {
mem_data->write_u64(mem_addr, rt_value.as_u64());
towrite_val = 0;
} else {
towrite_val = 1;
}
break;
case AC_FISRT_AMO_MODIFY32 ... AC_LAST_AMO_MODIFY32:
{
if (!memread || !memwrite) { break; }
int32_t fetched_value;
fetched_value = (int32_t)(mem_data->read_u32(mem_addr));
towrite_val = amo32_operations(memctl, fetched_value, rt_value.as_u32());
mem_data->write_u32(mem_addr, towrite_val.as_u32());
towrite_val = fetched_value;
break;
}
case AC_FISRT_AMO_MODIFY64 ... AC_LAST_AMO_MODIFY64:
{
if (!memread || !memwrite) { break; }
int64_t fetched_value;
fetched_value = (int64_t)(mem_data->read_u64(mem_addr));
towrite_val = (uint64_t)amo64_operations(memctl, fetched_value, rt_value.as_u64());
mem_data->write_u64(mem_addr, towrite_val.as_u64());
towrite_val = fetched_value;
break;
}
default: break;
}

Expand Down Expand Up @@ -275,8 +347,8 @@ DecodeState Core::decode(const FetchInterstage &dt) {
.excause = excause,
.ff_rs = FORWARD_NONE,
.ff_rt = FORWARD_NONE,
.alu_component
= (flags & IMF_MUL) ? AluComponent::MUL : AluComponent::ALU,
.alu_component = (flags & IMF_AMO) ? AluComponent::PASS :
(flags & IMF_MUL) ? AluComponent::MUL : AluComponent::ALU,
.aluop = alu_op,
.memctl = mem_ctl,
.num_rs = num_rs,
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2 changes: 2 additions & 0 deletions src/machine/core/core_state.h
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Expand Up @@ -4,6 +4,7 @@
#include "machinedefs.h"
#include "pipeline.h"
#include "common/memory_ownership.h"
#include "memory/address_range.h"

#include <QMap>
#include <cstdint>
Expand All @@ -14,6 +15,7 @@ namespace machine {

struct CoreState {
Pipeline pipeline = {};
AddressRange LoadReservedRange;
uint32_t stall_count = 0;
uint32_t cycle_count = 0;
};
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2 changes: 2 additions & 0 deletions src/machine/execute/alu.cpp
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Expand Up @@ -17,6 +17,8 @@ RegisterValue alu_combined_operate(
: alu64_operate(op.alu_op, modified, a, b);
case AluComponent::MUL:
return (w_operation) ? mul32_operate(op.mul_op, a, b) : mul64_operate(op.mul_op, a, b);
case AluComponent::PASS:
return a;
default: qDebug("ERROR, unknown alu component: %hhx", uint8_t(component)); return 0;
}
}
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1 change: 1 addition & 0 deletions src/machine/execute/alu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ namespace machine {
enum class AluComponent {
ALU, //> RV32/64I
MUL, //> RV32/64M
PASS, //> Pass operand A without change (used for AMO)
};

union AluCombinedOp {
Expand Down
110 changes: 109 additions & 1 deletion src/machine/instruction.cpp
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Expand Up @@ -106,6 +106,15 @@ bool argdesbycode_filled = fill_argdesbycode();
#define FLAGS_ALU_T_R_D (IMF_SUPPORTED | IMF_REGWRITE)
#define FLAGS_ALU_T_R_STD (FLAGS_ALU_T_R_D | IMF_ALU_REQ_RS | IMF_ALU_REQ_RT)

#define FLAGS_AMO_LOAD \
(FLAGS_ALU_I_LOAD | IMF_AMO)
// FLAGS_AMO_STORE for store conditional requires IMF_MEMREAD to ensure stalling because
// forwarding is not possible from memory stage after memory read, TODO to solve better way
#define FLAGS_AMO_STORE \
(FLAGS_ALU_I_STORE | FLAGS_ALU_T_R_D | IMF_AMO | IMF_MEMREAD)
#define FLAGS_AMO_MODIFY \
(FLAGS_ALU_I_LOAD | FLAGS_AMO_STORE | IMF_AMO)

#define NOALU \
{ .alu_op = AluOp::ADD }
#define NOMEM .mem_ctl = AC_NONE
Expand Down Expand Up @@ -143,10 +152,108 @@ struct InstructionMap {
#define IT_B Instruction::B
#define IT_U Instruction::U
#define IT_J Instruction::J
#define IT_AMO Instruction::AMO
#define IT_UNKNOWN Instruction::UNKNOWN

// clang-format off


// RV32/64A - Atomi Memory Operations

#define AMO_ARGS_LOAD {"d", "(s)"}
#define AMO_ARGS_STORE {"d", "t", "(s)"}
#define AMO_ARGS_MODIFY {"d", "t", "(s)"}

#define AMO_MAP_4ITEMS(NAME_BASE, CODE_BASE, MASK, MEM_CTL, FLAGS, ARGS) \
{ NAME_BASE, IT_AMO, NOALU, MEM_CTL, nullptr, ARGS , ((CODE_BASE) | 0x00000000), 0xfe00707f, { .flags = FLAGS}, nullptr}, \
{ NAME_BASE ".rl", IT_AMO, NOALU, MEM_CTL, nullptr, ARGS , ((CODE_BASE) | 0x02000000), 0xfe00707f, { .flags = FLAGS}, nullptr}, \
{ NAME_BASE ".aq", IT_AMO, NOALU, MEM_CTL, nullptr, ARGS , ((CODE_BASE) | 0x04000000), 0xfe00707f, { .flags = FLAGS}, nullptr}, \
{ NAME_BASE ".aqrl", IT_AMO, NOALU, MEM_CTL, nullptr, ARGS , ((CODE_BASE) | 0x06000000), 0xfe00707f, { .flags = FLAGS}, nullptr}

static const struct InstructionMap AMO_32_map[] = {
AMO_MAP_4ITEMS("amoadd.w", 0x0000202f, 0xfe00707f, AC_AMOADD32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
AMO_MAP_4ITEMS("amoswap.w", 0x0800202f, 0xfe00707f, AC_AMOSWAP32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
AMO_MAP_4ITEMS("lr.w", 0x1000202f, 0xfff0707f, AC_LR32, FLAGS_AMO_LOAD, AMO_ARGS_LOAD),
AMO_MAP_4ITEMS("sc.w", 0x1800202f, 0xfe00707f, AC_SC32, FLAGS_AMO_STORE, AMO_ARGS_STORE),
AMO_MAP_4ITEMS("amoxor.w", 0x2000202f, 0xfe00707f, AC_AMOXOR32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amoor.w", 0x4000202f, 0xfe00707f, AC_AMOOR32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amoand.w", 0x6000202f, 0xfe00707f, AC_AMOAND32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amomin.w", 0x8000202f, 0xfe00707f, AC_AMOMIN32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amomax.w", 0xa000202f, 0xfe00707f, AC_AMOMAX32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amominu.w", 0xc000202f, 0xfe00707f, AC_AMOMINU32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amomaxu.w", 0xe000202f, 0xfe00707f, AC_AMOMAXU32, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
};

static const struct InstructionMap AMO_64_map[] = {
AMO_MAP_4ITEMS("amoadd.d", 0x0000302f, 0xfe00707f, AC_AMOADD64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
AMO_MAP_4ITEMS("amoswap.d", 0x0800302f, 0xfe00707f, AC_AMOSWAP64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
AMO_MAP_4ITEMS("lr.d", 0x1000302f, 0xfff0707f, AC_LR64, FLAGS_AMO_LOAD, AMO_ARGS_LOAD),
AMO_MAP_4ITEMS("sc.d", 0x1800302f, 0xfe00707f, AC_SC64, FLAGS_AMO_STORE, AMO_ARGS_STORE),
AMO_MAP_4ITEMS("amoxor.d", 0x2000302f, 0xfe00707f, AC_AMOXOR64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amoor.d", 0x4000302f, 0xfe00707f, AC_AMOOR64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amoand.d", 0x6000302f, 0xfe00707f, AC_AMOAND64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amomin.d", 0x8000302f, 0xfe00707f, AC_AMOMIN64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amomax.d", 0xa000302f, 0xfe00707f, AC_AMOMAX64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amominu.d", 0xc000302f, 0xfe00707f, AC_AMOMINU64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
AMO_MAP_4ITEMS("amomaxu.d", 0xe000302f, 0xfe00707f, AC_AMOMAXU64, FLAGS_AMO_MODIFY, AMO_ARGS_MODIFY),
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN, IM_UNKNOWN,
};

static const struct InstructionMap AMO_map[] = {
IM_UNKNOWN,
IM_UNKNOWN,
{"amo-32", IT_R, NOALU, NOMEM, AMO_32_map, {}, 0x0002027, 0x0000707f, { .subfield = {7, 25} }, nullptr}, // OP-32
{"amo-64", IT_R, NOALU, NOMEM, AMO_64_map, {}, 0x0003027, 0x0000707f, { .subfield = {7, 25} }, nullptr}, // OP-32
IM_UNKNOWN,
IM_UNKNOWN,
IM_UNKNOWN,
IM_UNKNOWN,
IM_UNKNOWN,
};

#undef AMO_MAP_4ITEMS

static const struct InstructionMap LOAD_map[] = {
{"lb", IT_I, { .alu_op=AluOp::ADD }, AC_I8, nullptr, {"d", "o(s)"}, 0x00000003,0x0000707f, { .flags = FLAGS_ALU_I_LOAD }, nullptr}, // LB
{"lh", IT_I, { .alu_op=AluOp::ADD }, AC_I16, nullptr, {"d", "o(s)"}, 0x00001003,0x0000707f, { .flags = FLAGS_ALU_I_LOAD }, nullptr}, // LH
Expand Down Expand Up @@ -380,7 +487,7 @@ static const struct InstructionMap I_inst_map[] = {
{"store", IT_I, NOALU, NOMEM, STORE_map, {}, 0x23, 0x7f, { .subfield = {3, 12} }, nullptr}, // STORE
IM_UNKNOWN, // STORE-FP
IM_UNKNOWN, // custom-1
IM_UNKNOWN, // AMO
{"amo", IT_R, NOALU, NOMEM, AMO_map, {}, 0x2f, 0x7f, { .subfield = {3, 12} }, nullptr}, // OP-32
{"op", IT_R, NOALU, NOMEM, OP_map, {}, 0x33, 0x7f, { .subfield = {1, 25} }, nullptr}, // OP
{"lui", IT_U, { .alu_op=AluOp::ADD }, NOMEM, nullptr, {"d", "u"}, 0x37, 0x7f, { .flags = IMF_SUPPORTED | IMF_ALUSRC | IMF_REGWRITE }, nullptr}, // LUI
{"op-32", IT_R, NOALU, NOMEM, OP_32_map, {}, 0x3b, 0x7f, { .subfield = {1, 25} }, nullptr}, // OP-32
Expand Down Expand Up @@ -499,6 +606,7 @@ int32_t Instruction::immediate() const {
MASK(10, 21) << 1 | MASK(1, 20) << 11 | MASK(8, 12) << 12 | MASK(1, 31) << 20, 21);
break;
case ZICSR:
case AMO:
case UNKNOWN: break;
}
return ret;
Expand Down
4 changes: 3 additions & 1 deletion src/machine/instruction.h
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Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,8 @@ enum InstructionFlags : unsigned {
IMF_CSR = 1L << 20, /**< Implies csr read and write */
IMF_CSR_TO_ALU = 1L << 21, /**< Instruction modifies the current value */
IMF_ALU_RS_ID = 1L << 22,
// RV64/32A - Atomic Memory Operations
IMF_AMO = 1L << 23, /**< Instruction is AMO */
// TODO do we want to add those signals to the visualization?
};

Expand Down Expand Up @@ -108,7 +110,7 @@ class Instruction {
static const Instruction NOP;
static const Instruction UNKNOWN_INST;

enum Type { R, I, S, B, U, J, ZICSR, UNKNOWN };
enum Type { R, I, S, B, U, J, ZICSR, AMO, UNKNOWN };

/** Modified encoding to enable pseudoinstructions. */
enum class Modifier {
Expand Down
30 changes: 27 additions & 3 deletions src/machine/machinedefs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,15 +18,39 @@ enum AccessControl {
AC_U32,
AC_I64,
AC_U64,
AC_LOAD_LINKED,
AC_STORE_CONDITIONAL,
AC_LR32,
AC_SC32,
AC_AMOSWAP32,
AC_AMOADD32,
AC_AMOXOR32,
AC_AMOAND32,
AC_AMOOR32,
AC_AMOMIN32,
AC_AMOMAX32,
AC_AMOMINU32,
AC_AMOMAXU32,
AC_LR64,
AC_SC64,
AC_AMOSWAP64,
AC_AMOADD64,
AC_AMOXOR64,
AC_AMOAND64,
AC_AMOOR64,
AC_AMOMIN64,
AC_AMOMAX64,
AC_AMOMINU64,
AC_AMOMAXU64,
AC_CACHE_OP,
};

constexpr AccessControl AC_FIRST_REGULAR = AC_I8;
constexpr AccessControl AC_LAST_REGULAR = AC_U64;
constexpr AccessControl AC_FIRST_SPECIAL = AC_LOAD_LINKED;
constexpr AccessControl AC_FIRST_SPECIAL = AC_LR32;
constexpr AccessControl AC_LAST_SPECIAL = AC_CACHE_OP;
constexpr AccessControl AC_FISRT_AMO_MODIFY32 = AC_AMOSWAP32;
constexpr AccessControl AC_LAST_AMO_MODIFY32 = AC_AMOMAXU32;
constexpr AccessControl AC_FISRT_AMO_MODIFY64 = AC_AMOSWAP64;
constexpr AccessControl AC_LAST_AMO_MODIFY64 = AC_AMOMAXU64;

constexpr bool is_regular_access(AccessControl type) {
return AC_FIRST_REGULAR <= type and type <= AC_LAST_REGULAR;
Expand Down
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