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@SikoVerilog
SikoVerilog committed Dec 3, 2019
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23 changes: 12 additions & 11 deletions A5_1/A5_1.cache/wt/gui_handlers.wdf
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version:1
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9 changes: 5 additions & 4 deletions A5_1/A5_1.cache/wt/java_command_handlers.wdf
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version:1
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34 changes: 18 additions & 16 deletions A5_1/A5_1.cache/wt/webtalk_pa.xml
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Dec 3 14:38:44 2019">
<application name="pa" timeStamp="Tue Dec 3 17:02:10 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="1b4bc0e0d79f4bc4be5d727078e3462e" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
Expand All @@ -18,43 +18,45 @@ This means code written to parse this file will need to be revisited each subseq
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="2" type="JavaHandler"/>
<property name="CloseProject" value="8" type="JavaHandler"/>
<property name="CloseProject" value="9" type="JavaHandler"/>
<property name="EditUndo" value="1" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
<property name="ShowView" value="1" type="JavaHandler"/>
<property name="SimulationRun" value="20" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="1" type="JavaHandler"/>
<property name="SimulationRun" value="31" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="2" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="26" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="37" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="2" type="GuiHandlerData"/>
<property name="DefaultOptionPane_CLOSE" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="51" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="39" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="58" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="59" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="12" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="35" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="16" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="39" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="1" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="7" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="20" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="31" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="2" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="49" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="64" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="3" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="13" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="25" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="15" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="36" type="GuiHandlerData"/>
<property name="WaveformFindBar_CLOSE" value="1" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="16" type="GuiHandlerData"/>
<property name="WaveformOptionsView_RADIX" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="41" type="GuiMode"/>
<property name="GuiMode" value="42" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="34" type="TclMode"/>
<property name="TclMode" value="35" type="TclMode"/>
</item>
</section>
</application>
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2 changes: 1 addition & 1 deletion A5_1/A5_1.sim/sim_1/behav/xsim/compile.bat
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Expand Up @@ -6,7 +6,7 @@ REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Tue Dec 03 16:07:47 +0500 2019
REM Generated by Vivado on Tue Dec 03 16:47:44 +0500 2019
REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
REM
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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2 changes: 1 addition & 1 deletion A5_1/A5_1.sim/sim_1/behav/xsim/elaborate.bat
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Expand Up @@ -6,7 +6,7 @@ REM Filename : elaborate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Tue Dec 03 16:07:48 +0500 2019
REM Generated by Vivado on Tue Dec 03 16:47:45 +0500 2019
REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
REM
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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2 changes: 1 addition & 1 deletion A5_1/A5_1.sim/sim_1/behav/xsim/simulate.bat
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Expand Up @@ -6,7 +6,7 @@ REM Filename : simulate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
REM Generated by Vivado on Tue Dec 03 16:07:50 +0500 2019
REM Generated by Vivado on Tue Dec 03 16:47:46 +0500 2019
REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
REM
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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1575311936
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43
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1
186ba3cc3b824a018b5c0fd77cb249f1
8 changes: 4 additions & 4 deletions A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl
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webtalk_init -webtalk_dir C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Tue Dec 3 16:15:57 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Tue Dec 3 17:02:07 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2017.4 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2086221" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
Expand All @@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "b2af9c34-eb8a-4118-84dc-5a23d1b24676" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "186ba3cc3b824a018b5c0fd77cb249f1" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "42" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "47" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-6200U CPU @ 2.30GHz" -context "user_environment"
Expand All @@ -26,7 +26,7 @@ webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6940_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2793044498 -regid "" -xml C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_transmit -clientid 3134778748 -regid "" -xml C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate
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{
crc : 7582653859856289515 ,
crc : 5457501387071284239 ,
ccp_crc : 0 ,
cmdline : " -wto 186ba3cc3b824a018b5c0fd77cb249f1 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl" ,
buildDate : "Dec 15 2017" ,
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8 changes: 4 additions & 4 deletions A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsimkernel.log
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Running: xsim.dir/testbench_behav/xsimk.exe -simmode gui -wdb testbench_behav.wdb -simrunnum 0 -socket 51255
Running: xsim.dir/testbench_behav/xsimk.exe -simmode gui -wdb testbench_behav.wdb -simrunnum 0 -socket 51436
Design successfully loaded
Design Loading Memory Usage: 6120 KB (Peak: 6120 KB)
Design Loading CPU Usage: 15 ms
Design Loading Memory Usage: 6124 KB (Peak: 6124 KB)
Design Loading CPU Usage: 30 ms
Simulation completed
Simulation Memory Usage: 6940 KB (Peak: 6940 KB)
Simulation CPU Usage: 46 ms
Simulation CPU Usage: 62 ms
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2 changes: 1 addition & 1 deletion A5_1/A5_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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Dec 15 2017
21:07:18
C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.sim/sim_1/behav/xsim/glbl.v,1513215259,verilog,,,,glbl,,,,,,,,
C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.srcs/sim_1/imports/new/testbench.v,1575371233,verilog,,,,testbench,,,,,,,,
C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.srcs/sim_1/imports/new/testbench.v,1575373646,verilog,,,,testbench,,,,,,,,
C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.srcs/sources_1/imports/new/FIR_Para.v,1575371238,verilog,,C:/Users/Sanaullah/Documents/GitHub/Verilog/A5_1/A5_1.srcs/sim_1/imports/new/testbench.v,,FIR_Para,,,,,,,,
1 change: 1 addition & 0 deletions A5_1/A5_1.srcs/sim_1/imports/new/testbench.v
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Expand Up @@ -60,6 +60,7 @@ module testbench;
#20;

end
X = 'b0;
$fclose(file);
//$fclose(file1);
end
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2 changes: 1 addition & 1 deletion A5_1/A5_1.xpr
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<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="26"/>
<Option Name="WTXSimLaunchSim" Val="30"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
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