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Commits on Sep 10, 2023

• [-] Remove pullup constrains its break vivado build

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Commits on Jun 13, 2023

• [*] update readme

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Commits on Nov 23, 2021

• [-] Remove obsolete Zephyr description and images. Need to port from scratch to comply the latest risc-v specification

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Commits on Nov 21, 2021

• [!] Fix bootloader that cause incorrect behaviour on riscv-tests result output step. So now riscv-tests run succesfully on systemc model

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Commits on Jan 14, 2020

• [*] Generate and update Techical Reference Manual in pdf format

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Commits on Jan 7, 2020

• [*] Update and fix simulator for linux.

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Commits on Jan 2, 2020

• [*] Update readme after River upgrade. Achieved CPI=1.35; DMIPS per MHz=1.29

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Commits on Oct 16, 2019

• [!] fix link

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Commits on Sep 2, 2019

• [*] Update README with the new CPI score = 1.9 accordingly with dhrystone. Update River top level picture.

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Commits on Jul 2, 2019

• [*] Increase bootrom to 32KB to run extended FPU tests

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• [*] Update readme with the new link on demonstration video dualcore_river

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Commits on Dec 4, 2018

• [*] Update benchmark information in readme

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Commits on Nov 30, 2018

• [+] Add link to arm_vhdl repository

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Commits on Nov 29, 2018

• [!] Fix readme table

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• [!] Fix all bugs in ARM shit-register instructions

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Commits on Jul 22, 2018

• [*] Update README with the new benchmark results

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Commits on May 8, 2018

• [*] update README with C-examples description

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Commits on May 7, 2018

• [!] Fix README with changed project pathes

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Commits on Jan 2, 2018

• [+] Add pre-built zephyr and helloworld images using the latest GCC 7.1 with enabled C-extension.

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Commits on Jun 25, 2017

• [*] Preparing release v6.0

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Commits on Jun 19, 2017

• [*] update demo pictures and add example of debugging of FPGA with GNSS engine

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Commits on Mar 2, 2017

• [+] Add screenshot + description of debugging with symbols

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Commits on Feb 5, 2017

• [*] Update gh-pages with new documentation and fix links in readme

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Commits on Jan 29, 2017

• [+] Add 'democmd' into simple plugin example.

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Commits on Jan 28, 2017

• [*] benchmark results update

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Commits on Jan 27, 2017

• [!] Zephyr v1.6.0 run on FPGA and SystemC.

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Commits on Jan 26, 2017

• [-] Remove debug file generation in targets.

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Commits on Jan 19, 2017

• [*] Update 'rocket-chip' to the latest version. TileLink was totally redesigned.

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Commits on Jan 13, 2017

• [!] Fix links in readme.

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Commits on Jan 12, 2017

• [*] fix newlines in markdown

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• [*] Update readme.md before v5.0 release

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Commits on Dec 24, 2016

• [*] merging SystemC/VHDL with automatic comparision

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Commits on Dec 9, 2016

• [*] RIVER: Improving memory interface (+ 1.5 % to CPI).

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Commits on Dec 7, 2016

• [*] RIVER branch predictor improved by detecting 'ret' and 'jal' instructions that add +5 percentage to CPI.

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Commits on Oct 30, 2016

• [*] SystemC RIVER: several tests instructions executed: registers hazard and memory data load (LD) tested. DCache not entirely implemented yet.

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