Backend: fix ready timing from dispatch to frontend (OpenXiangShan#3127)

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -483,7 +483,7 @@ class CtrlBlockImp(
   )
 
   // pipeline between rename and dispatch
-  PipeGroupConnect(renameOut, dispatch.io.fromRename, s1_s3_redirect.valid, "renamePipeDispatch")
+  PipeGroupConnect(renameOut, dispatch.io.fromRename, s1_s3_redirect.valid, dispatch.io.toRenameAllFire, "renamePipeDispatch")
   dispatch.io.intIQValidNumVec := io.intIQValidNumVec
   dispatch.io.fpIQValidNumVec := io.fpIQValidNumVec
   dispatch.io.fromIntDQ.intDQ0ValidDeq0Num := intDq0.io.validDeq0Num

src/main/scala/xiangshan/backend/PipeGroupConnect.scala

@@ -8,6 +8,7 @@ class PipeGroupConnect[T <: Data](n: Int, gen: => T) extends Module {
     val in = Vec(n, Flipped(DecoupledIO(gen)))
     val out = Vec(n, DecoupledIO(gen))
     val flush = Input(Bool())
+    val outAllFire = Input(Bool())
   })
 
   // Input Alias
@@ -28,7 +29,7 @@ class PipeGroupConnect[T <: Data](n: Int, gen: => T) extends Module {
 
   // Todo: canAccVec for each elem
   // Todo: no outReadys version for better timing and lower performance
-  private[this] val canAcc = ((~valids).asUInt | outReadys).andR
+  private[this] val canAcc = io.outAllFire
 
   (validVec zip inValids.asBools zip outReadys.asBools).foreach { case ((valid, inValid), outReady) =>
     valid := MuxCase(
@@ -61,6 +62,7 @@ object PipeGroupConnect {
     left: Seq[DecoupledIO[T]],
     right: Vec[DecoupledIO[T]],
     flush: Bool,
+    rightAllFire: Bool,
     suggestName: String = null,
   ): Unit =  {
     require(left.size == right.size, "The sizes of left and right Vec Bundle should be equal in PipeGroupConnect")
@@ -72,6 +74,7 @@ object PipeGroupConnect {
       in.bits := left(i).bits
       left(i).ready := in.ready
     }
+    mod.io.outAllFire := rightAllFire
     right <> mod.io.out
 
     if (suggestName != null)

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -53,6 +53,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {
     val hartId = Input(UInt(hartIdLen.W))
     // from rename
     val fromRename = Vec(RenameWidth, Flipped(DecoupledIO(new DynInst)))
+    val toRenameAllFire = Output(Bool())
     // enq Rob
     val enqRob = Flipped(new RobEnqIO)
     // enq Lsq
@@ -192,7 +193,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {
   val isStore  = VecInit(io.fromRename.map(req => FuType.isStore(req.bits.fuType)))
   val isVStore = VecInit(io.fromRename.map(req => FuType.isVStore(req.bits.fuType)))
   val isAMO    = VecInit(io.fromRename.map(req => FuType.isAMO(req.bits.fuType)))
-  val isBlockBackward = VecInit(io.fromRename.map(_.bits.blockBackward))
+  val isBlockBackward  = VecInit(io.fromRename.map(x => x.valid && x.bits.blockBackward))
   val isWaitForward    = VecInit(io.fromRename.map(x => x.valid && x.bits.waitForward))
 
   val singleStepStatus = RegInit(false.B)
@@ -296,7 +297,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {
 
   // Only the uop with block backward flag will block the next uop
   val nextCanOut = VecInit((0 until RenameWidth).map(i =>
-    !(isBlockBackward(i) && io.fromRename(i).valid)
+    !isBlockBackward(i)
   ))
   val notBlockedByPrevious = VecInit((0 until RenameWidth).map(i =>
     if (i == 0) true.B
@@ -391,10 +392,12 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {
     * Part 4: send response to rename when dispatch queue accepts the uop
     */
   val hasValidInstr = VecInit(io.fromRename.map(_.valid)).asUInt.orR
-  val hasSpecialInstr = Cat((0 until RenameWidth).map(i => io.fromRename(i).valid && isBlockBackward(i))).orR
+  val hasSpecialInstr = Cat((0 until RenameWidth).map(i => isBlockBackward(i))).orR
 
   private val canAccept = !hasValidInstr || !hasSpecialInstr && io.enqRob.canAccept && dqCanAccept
 
+  val isWaitForwardOrBlockBackward = isWaitForward.asUInt.orR || isBlockBackward.asUInt.orR
+  io.toRenameAllFire := !isWaitForwardOrBlockBackward && io.enqRob.canAccept && dqCanAccept
   for (i <- 0 until RenameWidth) {
     io.fromRename(i).ready := thisCanActualOut(i) && io.enqRob.canAccept && dqCanAccept
 

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -299,7 +299,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
     intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i)
 
     // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready
-    io.in(i).ready := !hasValid || canOut
+    io.in(i).ready := canOut
 
     uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag})
     uops(i).instrSize := instrSizesVec(i)