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Commits on Jul 8, 2024

• vlenb: fix srcType assignment after convert to addi (OpenXiangShan#3151)

  Ziyue-Zhang

  authored
  828a8a4

• vperm: bump yunsuan, fix vl compute for vslideup (OpenXiangShan#3150)

  Ziyue-Zhang

  authored
  7cbc3b4

• IFU: cut the number of PC registers (OpenXiangShan#3103)

  Show description for e4d2f6a
  

  my-mayfly

  and

  zhou tao

  authored
  e4d2f6a

• LLPTW, RVH: fix the calculation of gpaddr that makes hgpaddr become x signal (OpenXiangShan#3156)

  Show description for 3211121
  pxk27

  authored
  3211121

• LLPTW, RVH: fix the bug that llptw doesn't resp L1TLB when hptw gaf or gpf happens (OpenXiangShan#3157)

  Show description for 69f13e8
  pxk27

  authored
  69f13e8

• HPTW, RVH: Fix flush condition (OpenXiangShan#3158)

  Show description for 1ae5db6
  

  pxk27

  and

  good-circle

  authored
  1ae5db6

Commits on Jul 5, 2024

• StandAloneDevice: use VerilogAXI4Record (OpenXiangShan#3147)

  Tang-Haojin

  authored
  4391123

• ci: fix vcs ci when it do not exit normally (OpenXiangShan#3141)

  Tang-Haojin

  authored
  823787d

Commits on Jul 4, 2024

• ClockGate: use VERILATOR_LEGACY for verilator version < 5 (OpenXiangShan#3133)

  Tang-Haojin

  authored
  8f9f96d

• top: implement XSNoCTop and standalone devices (OpenXiangShan#3136)

  Tang-Haojin

  authored
  720dd62

• CoupledL2: fix bug in RequestBuffer rdy update condition (OpenXiangShan#3146)

  linjuanZ

  authored
  0938652

• RenameTable: fix width of rename table addr ports (OpenXiangShan#3128)

  Show description for ad5c9e6
  Squareless-XD

  authored
  ad5c9e6

• csr: convert csrr vlenb instruction to a addi instruction (OpenXiangShan#3143)

  Show description for 63cb375
  Ziyue-Zhang

  authored
  63cb375

• backend: remove vector wakeup for fix timing (OpenXiangShan#3145)

  xiaofeibao-xjtu

  authored
  9994e74

• VsetModule: fix vlIsVlmax, checking tail should use max(VLMAX, VLEN/SEW) (OpenXiangShan#3135)

  sinsanction

  authored
  7994c93

• StoreQueue: Change timeout to an existing API(TimeOutAssert) implementation.

  

  Anzooooo

  authored and

  Tang-Haojin

  committed
  42d529e

• VLSU: fix the problem caused by the 'segmentUnit' not connecting with 'sbufferVecDifftestInfo'.

  

  Anzooooo

  authored and

  Tang-Haojin

  committed
  6edb148

• Parameters: Use uniform parameterized maximum values in VirtualLoadQueueSize and StoreQueueSize.

  

  Anzooooo

  authored and

  Tang-Haojin

  committed
  be867eb

• Dispatch2Iq: fix timing problem caused by bit width in 'Dispatch2iq'.

  

  Anzooooo

  authored and

  Tang-Haojin

  committed
  7a9ea6c

• Vfalu: add fflagsEn default value and fix vfredmin/max (OpenXiangShan#3137)

  Show description for ae44e2b
  lewislzh

  authored
  ae44e2b

• Backend: fix ready timing from dispatch to frontend (OpenXiangShan#3127)

  xiaofeibao-xjtu

  authored
  f5c1705

Commits on Jul 3, 2024

• rv64v: fix vwsll's imm read and illegal vsew check (OpenXiangShan#3131)

  Ziyue-Zhang

  authored
  4c8a449

• Configs: use DefaultConfig as KunminghuV2Config

  linjuanZ

  committed
  182b7ec

• CoupledL2: don't wait for PCredit if PCredit is already received

  linjuanZ

  committed
  5d15e43

• workflows: add CI job for CHI version

  linjuanZ

  committed
  70a669a

• SoC, Top: use Option for SoC widgets concerning L3

  linjuanZ

  committed
  1bf9a05

• workflows: add linux-hello-opensbi test case for CHI version

  linjuanZ

  committed
  02999db

• OpenLLC: add support for ReadNoSnp and WriteNoSnp

  linjuanZ

  committed
  81292e5

• SoC: an initial version of DummyLLC

  linjuanZ

  committed
  78a8cd2

Commits on Jul 2, 2024

• Makefile: prepend XSTOP_PREFIX to TOP (OpenXiangShan#3130)

  Tang-Haojin

  authored
  18179bb

• RVH, CSR: remove htimedelta for openSBI (OpenXiangShan#3125)

  Show description for a13f171
  cebarobot

  authored
  a13f171

• IssueQueue: change othersTransPolicy when allComp or allSimp for fix timing (OpenXiangShan#3120)

  xiaofeibao-xjtu

  authored
  b9631a8

• sim: use xs_assert_v2

  Tang-Haojin

  committed
  d4119b5

• make: generate seperated sv instead of aggregated verilog

  Tang-Haojin

  committed
  05b9cfb

• Top: use VerilogAXI4Record instead of sed to handle amba signal names

  Tang-Haojin

  committed
  2993c5e

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