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1. openlane openlane Public

   Forked from The-OpenROAD-Project/OpenLane

   OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

   Verilog

2. caravel_tinyriscv caravel_tinyriscv Public

   RISC-V based core

   Verilog 1