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  • Lampro Mellon

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  • caravel_tinyriscv Public

    RISC-V based core

    Verilog 1 Apache License 2.0 Updated Jan 4, 2021

  • openlane Public

    Forked from The-OpenROAD-Project/OpenLane

    OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

    Verilog Apache License 2.0 Updated Nov 30, 2020