Add support to continue in do while, add tests

Signed-off-by: Ryszard Rozak <[email protected]>

src/V3LinkJump.cpp

@@ -86,7 +86,7 @@ class LinkJumpVisitor final : public VNVisitor {
         } else if (VN_IS(nodep, DoWhile)) {
             // Handle it the same as AstWhile, because it will be converted to it
             if (endOfIter) {
-                underp = VN_AS(nodep, While)->stmtsp();
+                underp = VN_AS(nodep, DoWhile)->stmtsp();
             } else {
                 underp = nodep;
                 under_and_next = false;

test_regress/t/t_continue_do_while_bad.out

@@ -0,0 +1,6 @@
+%Warning-INFINITELOOP: t/t_continue_do_while_bad.v:14:7: Infinite loop (condition always true)
+   14 |       do begin
+      |       ^~
+                       ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest
+                       ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message.
+%Error: Exiting due to

test_regress/t/t_continue_do_while_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    expect_filename=>$Self->{golden_filename},
+    verilator_flags2=> ['--assert'],
+    fails => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_continue_do_while_bad.v

@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+
+   function void infinite_loop;
+      do begin
+         continue;
+      end
+      while (1);
+   endfunction
+
+   always @(posedge clk) begin
+      infinite_loop();
+      $stop;
+   end
+endmodule

test_regress/t/t_jumps_do_while.v

@@ -61,42 +61,113 @@ module t (/*AUTOARG*/
       while (1);
       return incr == 10;
    endfunction
-   // function bit test_5;
-   //    int incr = 0;
-   //    do begin
-   //       incr++;
-   //       continue;
-   //       incr++;
-   //    end
-   //    while (0);
-   //    return incr == 1;
-   //    endfunction
-
-   // function bit test_6;
-   //    int incr = 0;
-   //    do begin
-   //       incr++;
-   //       continue;
-   //       incr++;
-   //    end
-   //    while (incr < 5);
-   //    return incr == 5;
-   //    endfunction
-
-   // function bit test_7;
-   //    do begin
-   //       continue;
-   //    end
-   //    while (0);
-   //    return 1'b1;
-   //    endfunction
+
+   function bit test_6;
+      int incr = 0;
+      do begin
+         do begin
+            incr += 1;
+            incr += 2;
+         end
+         while (incr < 9);
+         incr++;
+         break;
+         incr++;
+      end
+      while (1);
+      return incr == 10;
+   endfunction
+
+   function bit test_7;
+      int incr = 0;
+      do begin
+         do begin
+            incr += 1;
+            break;
+            incr += 2;
+         end
+         while (incr < 9);
+         incr++;
+         break;
+         incr++;
+      end
+      while (1);
+      return incr == 2;
+   endfunction
+
+   function bit test_8;
+      int incr = 0;
+      do begin
+         incr++;
+         continue;
+         incr++;
+      end
+      while (0);
+      return incr == 1;
+   endfunction
+
+   function bit test_9;
+      int incr = 0;
+      do begin
+         incr++;
+         continue;
+         incr++;
+      end
+      while (incr < 5);
+      return incr == 5;
+   endfunction
+
+   function bit test_10;
+      do begin
+         continue;
+      end
+      while (0);
+      return 1'b1;
+   endfunction
+
+   function bit test_11;
+      int incr = 0;
+      do begin
+         do
+            incr++;
+         while (0);
+         incr++;
+         continue;
+         incr++;
+      end
+      while (incr < 11);
+      return incr == 12;
+   endfunction
+
+   function bit test_12;
+      int incr = 0;
+      do begin
+         do begin
+            incr++;
+            continue;
+            incr++;
+         end
+         while (0);
+         incr++;
+         continue;
+         incr++;
+      end
+      while (incr < 11);
+      return incr == 12;
+   endfunction
 
    always @(posedge clk) begin
-      if ({test_1(), test_2(), test_3(), test_4(), test_5()} == '1) begin
+      bit [11:0] results = {test_1(), test_2(), test_3(), test_4(), test_5(),
+                            test_6(), test_7(), test_8(), test_9(), test_10(),
+                            test_11(), test_12()};
+
+      if (results == '1) begin
          $write("*-* All Finished *-*\n");
          $finish;
       end
-      else
-        $stop;
+      else begin
+         $write("Results: %b\n", results);
+         $stop;
+      end
    end
 endmodule