Support sampling #14
Support sampling #14
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| vscp->fileline(), new AstVarRef(vscp->fileline(), newvscp, VAccess::WRITE), | ||
| new AstVarRef(vscp->fileline(), vscp, VAccess::READ)); | ||
| m_evalFuncp->addInitsp(finalp); | ||
| // |
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I don't think so, but it's placed here because it occurs in a corresponding place in the function used for clocks.
src/V3Clock.cpp
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| @@ -425,6 +447,26 @@ class ClockVisitor final : public VNVisitor { | |||
| addToEvalLoop(nodep); | |||
| } | |||
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| // Replace $sampled calls with sampling variables | |||
| virtual void visit(AstSampled* nodep) override { | |||
| m_inSampled = true; | |||
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Shouldn't we use VL_RESTORER here?
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Nice and simple, though one thing I'm worried about is how mergeable this is with the V5 branch. V3Clock changed significantly there, so it might be an issue. If you can, please put that code in a different pass. If not, I suggest to try and rebase it and see if it takes a significant effort. If so, we should consider doing it and opening a PR against V5.
test_regress/t/t_assert_past.pl
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| if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
| # DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
| # | ||
| # Copyright 2003-2009 by Wilson Snyder. This program is free software; you |
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| # Copyright 2003-2009 by Wilson Snyder. This program is free software; you | |
| # Copyright 2022 by Antmicro Ltd. This program is free software; you |
Same for the other test files.
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I've modified the licenses. When it comes to compatibility with V5 - I think the effort to glue it will be significant, so I'm looking for another pass that could contain that code.
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The change adds support for value sampling, i.e. access to values of expressions at the beginning of each time slot.
This is done with
$sampledfunction except for concurrent assertions where sampling is done by default.Before the change, the function was deleted during V3Assert pass when encountered in AST.
The change makes
$past,$fell,$rose,$stableand$changedrefer to sampled values, as expected by IEEE.The change can simplify implementation of explicit clocking for these functions, but such functionality is not added here.
Sampling is implemented in two stages:
$sampled.$sampledis replaced by their only subexpression, and for every variable in the subexpression:evalto occur at the beginning of every simulation step,The mechanic for that is based on the way such helper variables are created for clocks, in order to detect posedges/negedges.