ben-marshall
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A List of Free and Open Source Hardware Verification Tools and Frameworks
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awesome-semiconductor-startups Public
Forked from aolofsson/awesome-semiconductor-startupsList of awesome semiconductor startups
UpdatedApr 25, 2022 -
verilog-vcd-parser Public
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
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croyde-riscv Public
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
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uart Public
A simple implementation of a UART modem in Verilog.
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riscv-bitmanip Public
Forked from riscv/riscv-bitmanipWorking draft of the proposed RISC-V Bitmanipulation extension
Makefile Creative Commons Attribution 4.0 International UpdatedOct 8, 2021 -
configuration-structure Public
Forked from riscv/configuration-structureRISC-V Configuration Structure
C Creative Commons Attribution 4.0 International UpdatedOct 7, 2021 -
riscv-opcodes Public
Forked from riscv/riscv-opcodesRISC-V Opcodes
Python Other UpdatedAug 27, 2021 -
riscv-isa-sim Public
Forked from riscv-software-src/riscv-isa-simSpike, a RISC-V ISA Simulator
C Other UpdatedJul 30, 2021 -
SILVER Public
Forked from Chair-for-Security-Engineering/SILVERSILVER - Statistical Independence and Leakage Verification
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riscv-zkt-list Public
Forked from rvkrypto/riscv-zkt-listZkt "safe list": extension attests that the machine has data-independent execution time for these instructions
BSD 2-Clause "Simplified" License UpdatedApr 13, 2021 -
riscv-arch-test Public
Forked from riscv-non-isa/riscv-arch-testAssembly BSD 3-Clause "New" or "Revised" License UpdatedMar 30, 2021 -
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aes-sboxes Public
Somewhere to put different implementations of the AES SBox
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vanilla-riscv Public
Vanilla RISC-V core, implementing RV32IMC
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verilog-parser Public archive
A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
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microcoder Public
Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.
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riscv-multi-cycle Public
WIP - A multi-cycle implementation of the RISCV rv32ui architecture. *unverified, use PicoRV32 instead!*
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verilog-probe Public
A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.
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doxygen-themes Public
A collection of the various Doxygen Theme customisations I have created and used.
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sat-solver Public
A simple combinatorial boolean sat solver based on the AC-3 Algorithm
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verilog-doc Public
A basic documentation generator for Verilog, similar to Doxygen.
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verilog-dot Public
A simple dot file / graph generator for Verilog syntax trees.
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latex-boilerplate Public
A simple latex boilerplate with makefile for common commands.
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ann-playground Public
Code I develop while learning about Artificial Neural Networks
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cssbristol.github.io Public
Forked from cssbristol/cssbristol.co.ukSource code for the UoB Computer Science Society web portal
HTML MIT License UpdatedJan 15, 2016 -
tim Public
A small CPU core complete with compiler and ISA specification. Eventually....