Library Exchange Format (LEF) and Design Exchange Format (DEF)

Parsl - a Python parallel scripting library

Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.

Caliptra IP and firmware for integrated Root of Trust block

SystemVerilog synthesis tool

SystemC/TLM-2.0 Co-simulation framework

A Python package for creating and solving constrained randomization problems.

Basic SAT model of x86 instructions using Z3, autogenerated from Intel docs

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Control and status register code generator toolchain

HW Design Collateral for Caliptra RoT IP

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

SystemVerilog Functional Coverage for RISC-V ISA

A high-performance, zero-overhead, extensible Python compiler with built-in NumPy support

CherryUSB is a tiny and beautiful, portable and high performace USB host and device stack for embedded system with USB IP

A C++ to Verilog translation tool with some basic guarantees that your code will work.

List of awesome open source hardware tools, generators, and reusable designs

RISC-V Verification Interface

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Open source RTL simulation acceleration on commodity hardware

💎 A fast, open source text processor and publishing toolchain, written in Ruby, for converting AsciiDoc content to HTML 5, DocBook 5, and other formats.

Formal specification and verification of hardware, especially for security and privacy.

Multi-platform nightly builds of open source digital design and verification tools

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

Learn, share and collaborate on ASIC design using open tools and technologies

Documentation developer guide