Standard Cell Library based Memory Compiler using FF/Latch cells

Verilog library for ASIC and FPGA designers

支持AXI总线协议的8k×8 SP SRAM

ahb scram controller, design and verification

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

SRAM

Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

Simple sram controller in verilog.

An open-source static random access memory (SRAM) compiler.

数字IC相关资料

基于Clash Core 制作的Clash For Linux备份仓库 A Clash For Linux Backup Warehouse Based on Clash Core

Continuation of Clash Verge - A Clash Meta GUI based on Tauri (Windows, MacOS, Linux)

A web GUI client of Project V which supports VMess, VLESS, SS, SSR, Trojan, Tuic and Juicity protocols. 🚀

clash for windows汉化版. 提供clash for windows的汉化版, 汉化补丁及汉化版安装程序

Repository for LFS book translation (currently only Simplified Chinese).

一步一步写MIPS CPU

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