Fixed indentation

firmware/cpld/sgpio_if/top.vhd

@@ -30,13 +30,13 @@ entity top is
     Port(
         HOST_DATA       : inout std_logic_vector(7 downto 0);
         HOST_CAPTURE    : out   std_logic;
-		HOST_SYNC_CMD	: out	  std_logic;
-		HOST_SYNC			: in	  std_logic;
+        HOST_SYNC_CMD   : out   std_logic;
+        HOST_SYNC       : in    std_logic;
         HOST_DISABLE    : in    std_logic;
         HOST_DIRECTION  : in    std_logic;
         HOST_DECIM_SEL  : in    std_logic_vector(2 downto 0);
         HOST_Q_INVERT   : in    std_logic;
-           
+
         DA              : in    std_logic_vector(7 downto 0);
         DD              : out   std_logic_vector(9 downto 0);
 
@@ -58,17 +58,17 @@ architecture Behavioral of top is
 
     signal host_data_enable_i : std_logic;
     signal host_data_capture_o : std_logic;
-	signal host_sync_o : std_logic := '0';
-	signal host_sync_i : std_logic := '0';
-	signal host_sync_latched : std_logic := '0';
+    signal host_sync_o : std_logic := '0';
+    signal host_sync_i : std_logic := '0';
+    signal host_sync_latched : std_logic := '0';
 
     signal data_from_host_i : std_logic_vector(7 downto 0);
     signal data_to_host_o : std_logic_vector(7 downto 0);
 
     signal decimate_count : std_logic_vector(2 downto 0) := "111";
     signal decimate_sel_i : std_logic_vector(2 downto 0);
     signal decimate_en : std_logic;
-     
+
     signal q_invert : std_logic;
     signal rx_q_invert_mask : std_logic_vector(7 downto 0);
     signal tx_q_invert_mask : std_logic_vector(7 downto 0);
@@ -157,18 +157,18 @@ begin
             end if;
         end if;
     end process;
-	 
-	process (host_data_enable_i, host_sync_i)
-	begin
-		host_sync_o <= host_data_enable_i;
-		if host_data_enable_i = '1' then
-			if rising_edge(host_sync_i) then
-				host_sync_latched <= host_sync_i;
-			end if;
-		else
-			host_sync_latched <= '0';
-		end if;
-	end process;
+    
+    process (host_data_enable_i, host_sync_i)
+    begin
+        host_sync_o <= host_data_enable_i;
+        if host_data_enable_i = '1' then
+            if rising_edge(host_sync_i) then
+                host_sync_latched <= host_sync_i;
+            end if;
+        else
+            host_sync_latched <= '0';
+        end if;
+    end process;
 
     process(host_clk_i)
     begin
@@ -178,9 +178,9 @@ begin
                     host_data_capture_o <= host_data_enable_i and host_sync_latched;
                 end if;
             else
-					if codec_clk_i = '0' then
-						host_data_capture_o <= host_data_enable_i and decimate_en and host_sync_latched;
-					end if; 
+                if codec_clk_i = '0' then
+                    host_data_capture_o <= host_data_enable_i and decimate_en and host_sync_latched;
+                end if; 
             end if;
         end if;
     end process;