(Not official)

SoomRV with difftest

A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Criticality-aware Framework for Modeling Computer Performance

A flexible, high-performance, user-friendly computer architecture simulator engine

sniper for xiangshan multi core study

Neural Networks with low bit weights on low end 32 bit microcontrollers such as the CH32V003 RISC-V Microcontroller and others

linux kernel function callchain profiler

A Linux-capable RISC-V multicore for and by the world

This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dual-emission architecture.

Spike, a RISC-V ISA Simulator

RISC-V SoC designed by students in UCAS

Modern co-simulation framework for RISC-V CPUs

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Quick & Flexible Rack-Scale Computer Architecture Simulator