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GIKI-Tapeout_Saad_Khan Public
Forked from theuppercaseguy/GIKI-TapeoutA 8bit UART TRANSCIVER created and submited for FABRIAITION thorugh EFABLESS, marking GIK first ever Fabricated CHIP
Verilog Apache License 2.0 UpdatedJul 7, 2024 -
LLM4IC Public
Forked from DfX-NYUAD/LLM4ICLLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
UpdatedMay 17, 2024 -
Springschool-Supercomputing-and-Parallel-Programming Public
Forked from ucerd/Springschool-Supercomputing-and-Parallel-ProgrammingSupercomputing and Parallel Programming Spring School
C UpdatedMay 2, 2024 -
tiny-gpu Public
Forked from adam-maj/tiny-gpuA minimal GPU design in Verilog to learn how GPUs work from the ground up
SystemVerilog UpdatedMay 1, 2024 -
GIKI-TapeOut-2_huzaifa Public
Forked from HUZAIFA-TARIQ/GIKI-TapeOut-2TinyTapeout-DigitalClock
Verilog Apache License 2.0 UpdatedApr 21, 2024 -
RISCV_Single_Cycle_Core_MERL Public
Forked from merldsu/RISCV_Single_Cycle_CoreThis repository contains the design files of RISC-V Single Cycle Core
Verilog Apache License 2.0 UpdatedDec 14, 2023 -
chisel_labs_giki Public
These labs are based on Prof. Martin Shoeberl labs and intended as basic sessions to get one started with using Chisel with Nexys4 DDR FPGA board.
Tcl UpdatedSep 27, 2023 -
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xup_high_level_synthesis_design_flow Public
Forked from Xilinx/xup_high_level_synthesis_design_flowAMD Xilinx University Program HLS tutorial
C MIT License UpdatedSep 24, 2023 -
nexys4ddr_sevensegment Public
This repository is based on the labs developed by Prof. Martin Shoeberl and uses Chisel for digital design. I have added the seven segment decoder and a hex up counter that prints the values on the…
Tcl UpdatedSep 19, 2023 -
A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations
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chisel-book Public
Forked from schoeberl/chisel-bookDigital Design with Chisel
TeX UpdatedAug 3, 2023 -
hls4ml-tutorial Public
Forked from fastmachinelearning/hls4ml-tutorialTutorial notebooks for hls4ml
Jupyter Notebook UpdatedAug 1, 2023 -
Vitis_Embedded_Platform_Source Public
Forked from Xilinx/Vitis_Embedded_Platform_SourceTcl UpdatedJul 13, 2023 -
Vitis-Tutorials Public
Forked from Xilinx/Vitis-TutorialsVitis In-Depth Tutorials
C MIT License UpdatedJul 6, 2023 -
UETRV-PCore Public
Forked from ee-uet/UETRV-PCoreLinux Capable 32-bit RISC-V based SoC
SystemVerilog Apache License 2.0 UpdatedJul 5, 2023 -
rvalp Public
Forked from johnwinans/rvalpRISC-V Assembly Language Programming
TeX Creative Commons Attribution 4.0 International UpdatedJun 12, 2023 -
Vitis_Accel_Examples Public
Forked from Xilinx/Vitis_Accel_ExamplesVitis_Accel_Examples
Makefile Other UpdatedJun 5, 2023 -
chisel-lab Public
Forked from schoeberl/chisel-labLab exercises for Chisel in the digital electronics 2 course at DTU
Scala BSD 2-Clause "Simplified" License UpdatedMay 18, 2023 -
RISCV_Single_Cycle_Core Public
Forked from gareththomasnz/RISCV_Single_Cycle_CoreThis repository contains the design files of RISC-V Single Cycle Core
Verilog Apache License 2.0 UpdatedMay 11, 2023 -
RISCV_Pipeline_Core_MERL Public
Forked from merldsu/RISCV_Pipeline_CoreThis repository contains the design files of RISC-V Pipeline Core
Verilog Apache License 2.0 UpdatedMay 11, 2023 -
Vitis-HLS-Introductory-Examples Public
Forked from Xilinx/Vitis-HLS-Introductory-ExamplesC++ Other UpdatedMay 4, 2023 -
sky130_blender_renders_tutorial Public
Forked from mbalestrini/sky130_blender_renders_tutorialUpdatedOct 6, 2022 -
skywater_synopsysdb Public
This repository contains the various steps that shall enable one to convert the skywater 130nm library to the db format to be used in Synopsys design compiler.
1 UpdatedAug 11, 2022 -
skywaterlib-synopsysdb Public
Forked from KashifInayat/skywaterlib-synopsysdbShell Apache License 2.0 UpdatedAug 11, 2022 -
This repository contains part of our work done to infer power intent at a higher level of abstraction i.e. at the system-level. The designs span from simpler basic computing blocks to more practica…
Verilog UpdatedAug 7, 2022 -
skywater-pdk Public
Forked from google/skywater-pdkOpen source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Python Apache License 2.0 UpdatedJul 20, 2022 -
OpenSTA Public
Forked from The-OpenROAD-Project/OpenSTAOpenSTA engine
C++ GNU General Public License v3.0 UpdatedJul 12, 2022 -
OpenLane Public
Forked from efabless/OpenLaneThis repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components i…
Verilog Apache License 2.0 UpdatedJul 1, 2022 -
chipyard Public
Forked from ucb-bar/chipyardAn Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
C BSD 3-Clause "New" or "Revised" License UpdatedJun 18, 2022