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Commits on Sep 17, 2021

• verilog black box ports unknown/loads

  Show description for 85f437b
  jjcherry56

  committed
  85f437b

Commits on Jul 9, 2021

• read_verilog/link_design support redirection

  jjcherry56

  committed
  8c23d8e

Commits on Jul 7, 2021

• read_verilog no warn on pg_pin connections

  jjcherry56

  committed
  b9116bd

Commits on Jun 25, 2021

• update copyright

  jjcherry56

  committed
  2e8f003

Commits on Feb 19, 2021

• write_verilog w/o -include_pwr_gnd exclude top pwr/gnd port and dcl

  jjcherry56

  committed
  61df237

Commits on Feb 7, 2021

• leaks

  jjcherry56

  committed
  6359bd6

Commits on Jan 19, 2021

• write_verilog wire stmts

  jjcherry56

  committed
  d00937f

• issue#31 verilog concat assign

  jjcherry56

  committed
  c13383f

Commits on Jan 5, 2021

• mv debug_on into Debug

  jjcherry56

  committed
  54dbbf6

Commits on Dec 29, 2020

• rm Debug::print

  jjcherry56

  committed
  9b1dc88

Commits on Dec 25, 2020

• error/warn

  jjcherry56

  committed
  ee86a30

Commits on Dec 23, 2020

• cmd filename args with spaces

  jjcherry56

  committed
  1a99dd0

Commits on Dec 14, 2020

• error/warn IDs

  jjcherry56

  committed
  78d29c8

Commits on Nov 11, 2020

• flex disable register decls

  jjcherry56

  committed
  b4851a6

Commits on Nov 10, 2020

• disable flex register warnings

  jjcherry56

  committed
  c9296a0

Commits on Oct 20, 2020

• write_verilog -remove_cells

  jjcherry56

  committed
  01a1ab6

• write_verilog -include_pwr_gnd

  jjcherry56

  committed
  fc279f0

Commits on Sep 17, 2020

• flex disable register declarations

  jjcherry56

  committed
  7d31cfa

Commits on Jul 18, 2020

• VerilogWriter using instead of include for LibertyCell

  jjcherry56

  committed
  1c8f1ec

Commits on Jul 15, 2020

• write_verilog remove_cells use std::vector

  jjcherry56

  committed
  a5722ae

• write_verilog -remove_cells

  jjcherry56

  committed
  4fa9e46

Commits on Jul 3, 2020

• write_verilog power/ground port dcls

  jjcherry56

  committed
  e7ed317

Commits on May 5, 2020

• verilog port input tri -> input

  jjcherry56

  committed
  a862935

Commits on Apr 5, 2020

• verilog read/write to public includes

  jjcherry56

  committed
  ec85689

• public headers in include/sta

  jjcherry56

  committed
  ee326f1

• mv public headers to include/sta

  jjcherry56

  committed
  804953e

Commits on Mar 7, 2020

• update copyright

  jjcherry56

  committed
  4a017e8

Commits on Feb 16, 2020

• comment

  jjcherry56

  committed
  88c9cd3

• use #pragma once

  jjcherry56

  committed
  3d6d6e9

Commits on Feb 2, 2020

• use range iter

  jjcherry56

  committed
  7fdeb0d

Commits on Feb 1, 2020

• verilog reader make instances with liberty cell

  jjcherry56

  committed
  26c76cd

Commits on Jan 25, 2020

• UseSWIG cmake support for swig

  jjcherry56

  committed
  1068813

Commits on Jan 5, 2020

• flush Makefile.am

  jjcherry56

  committed
  d22eaea

Commits on Jul 4, 2019

• write_verilog escaped bus port name "input [7:0] \in[0] ;"

  jjcherry56

  committed
  74e287a

Commits on Jul 2, 2019

• VerilogWriter use liberty bus port order

  jjcherry56

  committed
  7af6906

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