remove inversion logic, test repeated drive & reset

hdl-util · Mar 1, 2021 · baef3ea · baef3ea
1 parent 510f791
commit baef3ea
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Showing 2 changed files with 46 additions and 33 deletions.
diff --git a/src/unipolar_rz.sv b/src/unipolar_rz.sv
@@ -13,15 +13,12 @@ module unipolar_rz #(
     // in seconds
     parameter real ONE_HIGH_TIME,
     // in seconds
-    parameter real RESET_TIME,
-    // Conventionally 0 = GND and 1 = VCC.
-    // Maybe your application is different!
-    parameter bit INVERT = 0
+    parameter real RESET_TIME
 ) (
     input logic clock,
     input logic [DATA_WIDTH-1:0] data,
     input logic enable,
-    output logic line = INVERT,
+    output logic line = 1'd0,
     output logic ready
 );
 
@@ -62,36 +59,36 @@ begin
     // odd state, driving high part of bit
     else if (state[0])
     begin
-        line <= !INVERT;
+        line <= 1'd1;
         state <= state + 1'd1;
-        time_counter <= (INVERT ? !internal_data[0] : internal_data[0]) ? ONE_HIGH : ZERO_HIGH;
+        time_counter <= internal_data[0] ? ONE_HIGH : ZERO_HIGH;
     end
     // even state, driving low part of bit
     else if (!state[0])
     begin
-        line <= INVERT;
+        line <= 1'd0;
         if (state == STATE_WIDTH'(2 * DATA_WIDTH))
         begin
             // pipelining to go direct to transmitting next data
             if (enable)
             begin
                 internal_data <= data;
                 state <= STATE_WIDTH'(1);
-                time_counter <= (INVERT ? !internal_data[0] : internal_data[0]) ? ONE_LOW : ZERO_LOW;
+                time_counter <= internal_data[0] ? ONE_LOW : ZERO_LOW;
             end
             // otherwise need to settle state with a reset
             else
             begin
                 internal_data <= 1'bx;
                 state <= STATE_WIDTH'(0);
-                time_counter <= RESET + ((INVERT ? !internal_data[0] : internal_data[0]) ? ONE_LOW : ZERO_LOW) + TIME_COUNTER_WIDTH'(1);
+                time_counter <= RESET + (internal_data[0] ? ONE_LOW : ZERO_LOW) + TIME_COUNTER_WIDTH'(1);
             end
         end
         else
         begin
             internal_data <= internal_data >> 1;
             state <= state + 1'd1;
-            time_counter <= (INVERT ? !internal_data[0] : internal_data[0]) ? ONE_LOW : ZERO_LOW;
+            time_counter <= internal_data[0] ? ONE_LOW : ZERO_LOW;
         end
     end
 end

diff --git a/test/sk6805_tb.sv b/test/sk6805_tb.sv
@@ -32,9 +32,16 @@ module sk6805_tb (
     localparam int SHIFT_OUT_COUNT = 4;
     int shift_out_counter = SHIFT_OUT_COUNT;
 
+    localparam int UPDATE_COUNT = 10;
+    int update_counter = UPDATE_COUNT;
+
     always_ff @(posedge clock)
     begin
-        if (ready && shift_out_counter > 0)
+        if (update_counter == 0)
+        begin
+            enable <= 1'd0;
+        end
+        else if (ready && shift_out_counter > 0)
         begin
             if (shift_out_counter != SHIFT_OUT_COUNT)
                 data <= data + 1;
@@ -55,48 +62,57 @@ module sk6805_tb (
             enable <= 1'd0;
             assert (sk6805.state == 0) else $fatal("not in expected state: %d", sk6805.state);
             assert (sk6805.time_counter == 0) else $fatal("did not reset");
+            shift_out_counter <= SHIFT_OUT_COUNT;
+            update_counter <= update_counter - 1;
         end
         else
         begin
             enable <= 1'd0;
         end
     end
 
-    int i, j;
+    int i, j, k;
     realtime now, high_time, low_time;
     logic [DATA_WIDTH-1:0] current_data = INITIAL_DATA;
     initial
     begin
         $timeformat(-9, 2, "ns");
         wait (!line);
-        for (i = 0; i < SHIFT_OUT_COUNT; i++)
+        for (i = 0; i < UPDATE_COUNT; i++)
         begin
-            for (j = 0; j < DATA_WIDTH; j++)
+            for (j = 0; j < SHIFT_OUT_COUNT; j++)
             begin
-                wait (line);
-                now = $realtime;
-                wait (!line);
-                high_time = $realtime - now;
-                now = $realtime;
-                if (high_time == 600)
+                for (k = 0; k < DATA_WIDTH; k++)
                 begin
-                    // one
-                    assert (current_data[j]) else $fatal("Unexpected 1 for %h @ %d, %d", current_data, i, j);
+                    wait (line);
+                    now = $realtime;
+                    wait (!line);
+                    high_time = $realtime - now;
+                    now = $realtime;
+                    if (high_time == 600)
+                    begin
+                        // one
+                        assert (current_data[k]) else $fatal("Unexpected 1 for %h @ %d, %d, %d", current_data, i, j, k);
+                    end
+                    else if (high_time == 300)
+                    begin
+                        // zero
+                        assert (!current_data[k]) else $fatal("Unexpected 0 for %h @ %d, %d, %d", current_data, i, j, k);
+                    end
+                    else
+                    begin
+                        $fatal("unexpected tHIGH = %t", high_time);
+                    end
                 end
-                else if (high_time == 300)
-                begin
-                    // zero
-                    assert (!current_data[j]) else $fatal("Unexpected 0 for %h @ %d, %d", current_data, i, j);
-                end
-                else
+
+                if (j != SHIFT_OUT_COUNT - 1)
                 begin
-                    $fatal("unexpected tHIGH = %t", high_time);
+                    current_data = current_data + 1;
                 end
             end
-            current_data  = current_data + 1;
+            wait(ready && clock);
+            assert(($realtime - now) == 80190) else $fatal("did not reset");
         end
-        wait(ready && clock);
-        assert(($realtime - now) == 80190) else $fatal("did not reset");
         $finish;
     end
 endmodule