GitHub - kass-andra-go/school_synth_homework_4: My solution of homework #4 of chipdesignschool 2023/2024. https://github.com/chipdesignschool/systemverilog-homework

This is my solution of homework #4 of Chip Desing School 2023/2024. The task is located here https://github.com/chipdesignschool/systemverilog-homework.

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
04_07_formula_1_pipe.sv		04_07_formula_1_pipe.sv
04_08_formula_1_pipe_aware_fsm.sv		04_08_formula_1_pipe_aware_fsm.sv
04_08_formula_1_pipe_aware_fsm_var_2.sv		04_08_formula_1_pipe_aware_fsm_var_2.sv
04_09_shift_register_with_valid.sv		04_09_shift_register_with_valid.sv
README.md		README.md
formula_1_pipe_aware_fsm_top_copy.sv		formula_1_pipe_aware_fsm_top_copy.sv
formula_1_pipe_with_shift_reg.sv		formula_1_pipe_with_shift_reg.sv
isqrt.sv		isqrt.sv
isqrt_slice_comb.sv		isqrt_slice_comb.sv
isqrt_slice_reg.sv		isqrt_slice_reg.sv
tb_shift_reg.sv		tb_shift_reg.sv
tb_shift_reg_v2.sv		tb_shift_reg_v2.sv
testbench_formula_1_pipe.sv		testbench_formula_1_pipe.sv
testbench_formula_1_pipe_aware_fsm.sv		testbench_formula_1_pipe_aware_fsm.sv

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