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Telecommunications Engineer & HDL designer
- Tornquist, Argentina
- linkedin.com/in/leandro-echevarria/
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verilog-axis Public
Forked from alexforencich/verilog-axisVerilog AXI stream components for FPGA implementation
Python MIT License UpdatedMar 31, 2023 -
fusesoc Public
Forked from olofk/fusesocPackage manager and build abstraction tool for FPGA/ASIC development
Python BSD 2-Clause "Simplified" License UpdatedMar 7, 2023 -
RALBot-header Public
Forked from Julian-DD/RALBot-header🪲Generate C/Verilog header file from compiled SystemRDL input
Python UpdatedJan 26, 2023 -
readme-chess Public template
Forked from marcizhu/readme-chess♟️ Play Multiplayer Chess in a README file!
Python MIT License UpdatedJul 6, 2022 -
chisel-tutorial Public
Forked from ucb-bar/chisel-tutorialchisel tutorial exercises and answers
Scala Other UpdatedJan 6, 2022