Fixed point math library for SystemVerilog

SystemVerilog parser library fully compliant with IEEE 1800-2017

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

uvm AXI BFM(bus functional model)

Betelgeuse Supernova Twitter Bot

YosysHQ SVA AXI Properties

An open source, parameterized SystemVerilog digital hardware IP library

FPGA board-level debugging and reverse-engineering tool

SystemVerilog linter

Here you will find documentation, demos and basic support for this board, developed by INTI - CMNB and Emtech as part of the CIAA project.

Open source FPGA-based NIC and platform for in-network compute

📚 Modern C++ Tutorial: C++11/14/17/20 On the Fly | https://changkun.de/modern-cpp/