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1. Digital-Outlet-Timer Digital-Outlet-Timer Public

   Firmware for the Digital Outlet Timer Project

   C++

2. 5-Stage-Pipelined-Processor 5-Stage-Pipelined-Processor Public

   Modules used for implementing a 5 stage pipelined MIPS processor capable of implementing basic R, I, and J type instructions

   Verilog

3. FPGA-Clock FPGA-Clock Public

   A clock implemented using the Basys 3 board. Has an alarm and ability to set the time.

   Verilog

4. Verilog-Synth-Simulation Verilog-Synth-Simulation Public

   A verilog synthesizer made solely for simulation but not synthesis on fpga

   Verilog

5. Embedded-Lab-Projects Embedded-Lab-Projects Public

   A series of lab projects for introduction to embedded systems programming

6. UART_Project UART_Project Public

   UART Receive and Transmit Module built in Verilog and Synthesized onto the Basys3 FPGA board

   Verilog