UART Receive and Transmit Module built in Verilog and Synthesized onto the Basys3 FPGA board
Top is the top module which houses the other 2 inside of it. This project was demonstarted using Putty. A character was pressed on the keyboard of the connected computers keyboard. The programmed FPGA would then receive the data for the character and send it back, and it would then be visible on the opened terminal.