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axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedJan 16, 2024 -
pulp Public
Forked from pulp-platform/pulpThis is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
SystemVerilog Other UpdatedOct 5, 2023 -
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pulpissimo Public
Forked from pulp-platform/pulpissimoThis is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
SystemVerilog Other UpdatedFeb 13, 2023 -
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cortexm0ds Public
Forked from ForrestBlue/cortexm0dssimple AMBA systems reference
Verilog UpdatedJan 19, 2016