Skip to content
View maj77's full-sized avatar

Block or report maj77

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. DCFD DCFD Public

    Implementation of digital constant fraction discriminator on FPGA

    SystemVerilog

  2. Karatsuba_project Karatsuba_project Public

    Hardware implementation of Karatsuba multiplication algorithm

    Verilog 1

  3. 16bitCounter 16bitCounter Public

    Assembly

  4. VGA_CONTROLLER VGA_CONTROLLER Public

    VGA controller equipped with UART receiver

    VHDL

  5. IC_design_lab IC_design_lab Public

    Verilog

  6. SISK_lab SISK_lab Public

    C