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Focusing
Digital Design Engineer doing ASIC design from 9 to 5. Enthusiastic about computer architecture, low level programming, DSP and FPGAs.
- Novi Sad
- in/milannedic
Highlights
- Pro
Popular repositories Loading
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zedboard_axi4_master_burst_example
zedboard_axi4_master_burst_example PublicForked from k0nze/zedboard_axi4_master_burst_example
Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
Verilog
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libsystemctlm-soc
libsystemctlm-soc PublicForked from Xilinx/libsystemctlm-soc
SystemC/TLM-2.0 Co-simulation framework
Verilog
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PYNQ_Composable_Pipeline
PYNQ_Composable_Pipeline PublicForked from Xilinx/PYNQ_Composable_Pipeline
PYNQ Composabe Overlays
Tcl
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kv260_imx219_to_displayport
kv260_imx219_to_displayport PublicForked from gtaylormb/ultra96v2_imx219_to_displayport
Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
Tcl
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MSREAL
MSREAL PublicForked from DjordjeMiseljic/MSREAL
Ovaj repozitorijum ce obuhvatati sav materijal koji je potreban za laboratorijske vezbe predmeta MSREAL.
C
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