UVM register utility generation by inputting xls table

Environment Modules: provides dynamic modification of a user's environment

Synopsys License patcher

There is segmentation fault of VCS which should be fixed.

Verilog PCI express components

OpenTitan: Open source silicon root of trust

Random instruction generator for RISC-V processor verification

Awesome ASIC design verification

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

Rocket Chip Generator

Auto-complete VIM script tailored for those who cannot use a keyboard for long periods of time (RSI).

Resources for Python Crash Course, from No Starch Press.

Online resources for Python Crash Course, 3rd edition, from No Starch Press.

Online resources for Python Crash Course (Second Edition), from No Starch Press

《Python Cookbook》 3rd Edition Translation

《Python Cookbook》 3rd Edition Translation

Novel GUI Based UVM Testbench Template Builder

highlighting match of matchit.vim

A flexible test harness designed for scientific application development.

Build a UVM Environment for an parametrized memory module, including uvm testbench architecture components such as; sequencer, driver, monitor, scoreboard and subscriber. design was verified using …

Code generation tool for control and status registers

UVM 1.2 port to Python

UVM Register Agent used with the gen_regs flow

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

🐌Yet Another Simulation Architecture

SystemRDL 2.0 language compiler front-end

Functional verification project for the CORE-V family of RISC-V cores.

DOULOS Easier UVM Code Generator

Fully parametrizable combinatorial parallel LFSR/CRC module