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Commits on Sep 23, 2021

• Integer SRT16 Divider (OpenXiangShan#1019)

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  notlqr

  authored
  a58e335

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Commits on Jul 28, 2021

• Update difftest to use NEMU master branch (OpenXiangShan#902)

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  AugustusWillisWang

  authored
  a3e8760

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Commits on Jul 24, 2021

• misc: update PCL information (OpenXiangShan#899)

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  poemonsense

  authored
  f320e0f

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Commits on Jun 4, 2021

• Add MulanPSL-2.0 License (OpenXiangShan#824)

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  Lemover

  authored
  c6d4398

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Commits on Feb 1, 2021

• Merge remote-tracking branch 'origin/master' into mem-timing

  AugustusWillisWang

  committed
  53c7ab8

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• chore: update debug script

  AugustusWillisWang

  committed
  3802dba

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Commits on Jan 25, 2021

• Merge branch 'master' of github.com:RISCVERS/XiangShan into L1DCacheReTest

  njuallen

  committed
  2199a01

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Commits on Jan 13, 2021

• fix bug in core Agent

  BigWhiteDog

  committed
  b086c6d

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Commits on Dec 9, 2020

• fix peek poke ordering

  BigWhiteDog

  committed
  ab3aa7e

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Commits on Dec 1, 2020

• add icache uncache support

  jinyue110

  committed
  4b3d9f6

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Commits on Nov 8, 2020

• Merge branch 'master' into icache-l1plus

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  jinyue110

  committed
  a9ecfa6

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Commits on Nov 3, 2020

• icacheMissQueue: fix resp valid when needflush bug

  jinyue110

  committed
  043203e

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• icache: pipeline still going after branch flush

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  jinyue110

  committed
  b6f269e

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Commits on Nov 2, 2020

• Merge 'master' into 'xs-fpu'

  ljwljwljwljw

  committed
  3136ee6

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Commits on Oct 31, 2020

• L1plusCache: fix bug that flush didn't change valid_array

  jinyue110

  committed
  598e480

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Commits on Oct 30, 2020

• PASS coremark and microbench but loader(fence.i) FAIL

  jinyue110

  committed
  b7959e5

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• connect l1pluscache into memory hierarchy

  jinyue110

  committed
  6f763b2

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Commits on Oct 29, 2020

• Merge branch 'master' into icache-missqueue

  jinyue110

  committed
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Commits on Oct 28, 2020

• Merge remote-tracking branch 'origin/fix-modulename-in-chiseltest' into update-chisel

  ljwljwljwljw

  committed
  5873524

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Commits on Oct 24, 2020

• PrintModuleName: must run after wiring transform

  ljwljwljwljw

  committed
  903af6a

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Commits on Oct 21, 2020

• icacheMissQueue: support different client visit

  jinyue110

  committed
  8495949

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• [WIP] Lsq: fix stq forward & rollback logic

  AugustusWillisWang

  committed
  e1f91fc

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Commits on Oct 20, 2020

• icacheMissQueue: done and PASS coremark and microbench

  jinyue110

  committed
  3c20517

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• icacheMissQueue: fix bug that s_write_back deadlock

  jinyue110

  committed
  118c6c3

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Commits on Oct 19, 2020

• icacheMissQueue: add debug info and fix deadlock bug

  jinyue110

  committed
  a684b6f

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• icacheMissQueue: fix syntax bug

  jinyue110

  committed
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Commits on Oct 15, 2020

• debug/Makefile: keep it clean

  ljwljwljwljw

  committed
  91e7291

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Commits on Oct 14, 2020

• BPU: ret instruction taken depend on btb hit when spec ras is empty

  jinyue110

  committed
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Commits on Sep 8, 2020

• icache: add mmio address surpport

  jinyue110

  committed
  0a019f1

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Commits on Sep 7, 2020

• Merge branch 'dev-icache' of https://github.com/RISCVERS/XiangShan into dev-icache

  jinyue110

  committed
  b21206a

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• icache: add performance counter

  jinyue110

  committed
  7ccd034

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• Merge branch 'l2cache' into dev-icache

  njuallen

  committed
  dbe8465

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• icache: fix some print error

  jinyue110

  committed
  5c97968

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Commits on Sep 4, 2020

• icache: add cutHelper

  jinyue110

  committed
  35727b1

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Commits on Sep 3, 2020

• Update unit test

  ljwljwljwljw

  committed
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