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  1. ChampSim-Branch-Predictor-simulator ChampSim-Branch-Predictor-simulator Public

    Forked from Priyanshumishra77/ChampSim-Branch-Predictor-simulator

    ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

    C++

  2. cocotb-for-koti cocotb-for-koti Public

    Forked from Priyanshumishra77/cocotb-for-kids

    Complete tutorial code.

    Verilog

  3. Design-and-UVM-TB-of-RISC-V-Microprocessor Design-and-UVM-TB-of-RISC-V-Microprocessor Public

    Forked from Priyanshumishra77/Design-and-UVM-TB-of-RISC-V-Microprocessor

    Design and UVM-TB of RISC -V Microprocessor

    SystemVerilog

  4. RISC-V-SUPERSCALAR-OoO RISC-V-SUPERSCALAR-OoO Public

    Forked from Priyanshumishra77/RISC-V-SUPERSCALAR-OoO

    DUTH RISC-V Superscalar Microprocessor

    SystemVerilog

  5. RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS Public

    Forked from Priyanshumishra77/RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS

    RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS

    Verilog

  6. RISCV-processor RISCV-processor Public

    Forked from Priyanshumishra77/RISCV-processor

    RISC-V SoC written in SystemVerilog

    SystemVerilog